x86 architecture
model specific registers


note: The model specific registers depend on the implementation.
 
Time Stamp Counter
 
name 6
3		   3
2		 3
1		   0
 
TSC
 
0000_0010h		  
time stamp counter value
 
 
TSC_ADJUST
 
0000_003Bh		  
time stamp counter adjustment
 
 
TSC_AUX
 
C000_0103h		 reserved  
processor ID value
 
 
TSC_DEADLINE
 
0000_06E0h (NS)		  
time stamp counter deadline
 
 
MPERF
 
0000_00E7h		  
maximum frequency clock count
 
 
APERF
 
0000_00E8h		  
actual frequency clock count
 


 
Feature Control
 
name 6
3		 6
2		 6
1		 6
0		 5
9		 5
8		 5
7		 5
6		 5
5		 5
4		 5
3		 5
2		 5
1		 5
0		 4
9		 4
8		 4
7		 4
6		 4
5		 4
4		 4
3		 4
2		 4
1		 4
0		 3
9		 3
8		 3
7		 3
6		 3
5		 3
4		 3
3		 3
2
3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
 
TR12
 
0000_000Eh		 reserved or used otherwise I
T
R		 reserved or
used otherwise
 
MISC_CTL
 
0000_0119h		 reserved or
used otherwise		 P
S
N
D		  
reserved or used otherwise
 
MISC_ENABLE
 
0000_01A0h		 reserved or used otherwise L1
IP
PR
D		 D
A
D		 L1
ST
PR
D		 res.
...		 X
D
D		 res.
...
reserved or
used otherwise		 L1
DC
CM		 ET
PR
D		 L
C
M
V		 F
PR
E		 GV
3
L		 A
S
P
D		 M
O
N
E		 BD
PH
E		 GV
3
E		 GV
1+
E		 ? T
M
2
E		 PE
BS
U		 B
T
S
U		 P
B
E		 P
Q
D		 S
L
E		 P
M
A		 L
3
D		 T
C
D		 S
L
D		 T
M
1
E		 F
C
E		 L
P
P
E		 F
S
E
 
MISC_FEAT_CTL
 
0000_01A4h		  
reserved or used otherwise
 		 L1
IP
PR
D		 L1
PR
D		 L2
AL
PR
D		 L2
PR
D
 
EFER
 
C000_0080h		 reserved or used otherwise M
C
O
M		 r. T
C
E		 F
FX
SR		 LM
SL
E		 S
V
M
E		 N
X
E		 L
M
A		   L
M
E		 reserved or
used otherwise		 S
C
E
 
PLATFORM_INFO
 
0000_00CEh		 CP
UI
DF
A		  
reserved or used otherwise
 
 
MISC_FEATURES
 
0000_0140h		  
reserved or used otherwise
 		 CP
UI
DF
E
 
SPEC_CTRL
 
0000_0048h (NS)		  
reserved or used otherwise
 		 S
S
B
D		 ST
I
B
P		 I
B
R
S
 
PRED_CMD
 
0000_0049h (NS) (WO)		  
reserved or used otherwise
 		 I
B
P
B
 
ARCH_CAPABILITIES
 
0000_010Ah (RO)		  
reserved or used otherwise
 		 T
A
A
NO		 T
S
X
Ctl		 IF
PC
MC
NO		 M
D
S
NO		 S
S
B
NO		 SK
L1
FL
VE		 R
S
B
A		 IB
RS
All		 RD
CL
NO
 
FLUSH_CMD
 
0000_010Bh (NS) (WO)		  
reserved or used otherwise
 		 L
1
D
FL
 
TSX_CTL
 
0000_0122h (NS)		  
reserved or used otherwise
 		 T
S
X
CC		 R
T
M
D
 
OPT_CTL
 
0000_0123h		  
reserved or used otherwise
 		 SR
B
DS
MD


 
SYSENTER and SYSEXIT
 
name 6
3		   3
2		 3
1		   1
6		 1
5		   0
 
SEP_SEL
 
0000_0174h		 ignored scratch base selector for
SYSENTER CS/SS and
SYSEXIT CS/SS
 
SEP_ESP
 
0000_0175h		  
ignored
 		  
target ESP
 
 
SEP_RSP
 
0000_0175h		  
target RSP
 
 
SEP_EIP
 
0000_0176h		  
ignored
 		  
target EIP
 
 
SEP_RIP
 
0000_0176h		  
target RIP
 

 
SYSCALL and SYSRET
 
name 6
3		   4
8		 4
7		   3
2		 3
1		   0
 
STAR
 
C000_0081h		 base selector for
SYSRET CS/SS		 base selector for
SYSCALL CS/SS		  
target EIP
 
 
LSTAR
 
C000_0082h		  
target RIP for PM64 callers
 
 
CSTAR
 
C000_0083h		  
target RIP for CM callers
 
 
FMASK
 
C000_0084h		 reserved  
RFLAGS mask for SYSCALL
 

 
FS base and GS base
 
name 6
3		   0
 
FS_BAS
 
C000_0100h		  
FS base
 
 
GS_BAS
 
C000_0101h		  
GS base
 
 
KERNEL_GS_BAS
 
C000_0102h		  
kernel GS base (for SWAPGS)
 


 
Memory Types
 
0 1 2 3 4 5 6 7
UC WC reserved reserved WT WP WB UC_WEAK
note PAT-only UC_WEAK can be overridden by WC from MTRRs

 
Page Attribute Table
 
name 6
3		 6
2		 6
1		 6
0		 5
9		 5
8		 5
7		 5
6		 5
5		 5
4		 5
3		 5
2		 5
1		 5
0		 4
9		 4
8		 4
7		 4
6		 4
5		 4
4		 4
3		 4
2		 4
1		 4
0		 3
9		 3
8		 3
7		 3
6		 3
5		 3
4		 3
3		 3
2
3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
PAT
 
0000_0277h		  
reserved
 		 PA7 reserved PA6 reserved PA5 reserved PA4
 
reserved
 		 PA3 reserved PA2 reserved PA1 reserved PA0

 
Memory Type Range Registers
 
name 6
3		 6
2		 6
1		 6
0		 5
9		 5
8		 5
7		 5
6		 5
5		 5
4		 5
3		 5
2		 5
1		 5
0		 4
9		 4
8		 4
7		 4
6		 4
5		 4
4		 4
3		 4
2		 4
1		 4
0		 3
9		 3
8		 3
7		 3
6		 3
5		 3
4		 3
3		 3
2
3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
MTRR_CAP
 
0000_00FEh		  
reserved
 
reserved S
M
R
R		 W
C		 r. F
I
X		 VCNT (n)
MTRR_DEF_TYPE
 
0000_02FFh		  
reserved
 
reserved E F
E		 res.  
TYPE
 

 
Fixed Range MTRRs
 
name 6
3		   5
6		 5
5		   4
8		 4
7		   4
0		 3
9		   3
2		 3
1		   2
4		 2
3		   1
6		 1
5		   8 7   0
 
MTRR_FIX_64K_00000
 
0000_0250h		 7_0000h
7_FFFFh		 6_0000h
6_FFFFh		 5_0000h
5_FFFFh		 4_0000h
4_FFFFh		 3_0000h
3_FFFFh		 2_0000h
2_FFFFh		 1_0000h
1_FFFFh		 0_0000h
0_FFFFh
 
MTRR_FIX_16K_80000
 
0000_0258h		 9_C000h
9_FFFFh		 9_8000h
9_BFFFh		 9_4000h
9_7FFFh		 9_0000h
9_3FFFh		 8_C000h
8_FFFFh		 8_8000h
8_BFFFh		 8_4000h
8_7FFFh		 8_0000h
8_3FFFh
 
MTRR_FIX_16K_A0000
 
0000_0259h		 B_C000h
B_FFFFh		 B_8000h
B_BFFFh		 B_4000h
B_7FFFh		 B_0000h
B_3FFFh		 A_C000h
A_FFFFh		 A_8000h
A_BFFFh		 A_4000h
A_7FFFh		 A_0000h
A_3FFFh
 
MTRR_FIX_4K_C0000
 
0000_0268h		 C_7000h
C_7FFFh		 C_6000h
C_6FFFh		 C_5000h
C_5FFFh		 C_4000h
C_4FFFh		 C_3000h
C_3FFFh		 C_2000h
C_2FFFh		 C_1000h
C_2FFFh		 C_0000h
C_0FFFh
 
MTRR_FIX_4K_C8000
 
0000_0269h		 C_F000h
C_FFFFh		 C_E000h
C_EFFFh		 C_D000h
C_DFFFh		 C_C000h
C_CFFFh		 C_B000h
C_BFFFh		 C_A000h
C_AFFFh		 C_9000h
C_9FFFh		 C_8000h
C_8FFFh
 
MTRR_FIX_4K_D0000
 
0000_026Ah		 D_7000h
D_7FFFh		 D_6000h
D_6FFFh		 D_5000h
D_5FFFh		 D_4000h
D_4FFFh		 D_3000h
D_3FFFh		 D_2000h
D_2FFFh		 D_1000h
D_2FFFh		 D_0000h
D_0FFFh
 
MTRR_FIX_4K_D8000
 
0000_026Bh		 D_F000h
D_FFFFh		 D_E000h
D_EFFFh		 D_D000h
D_DFFFh		 D_C000h
D_CFFFh		 D_B000h
D_BFFFh		 D_A000h
D_AFFFh		 D_9000h
D_9FFFh		 D_8000h
D_8FFFh
 
MTRR_FIX_4K_E0000
 
0000_026Ch		 E_7000h
E_7FFFh		 E_6000h
E_6FFFh		 E_5000h
E_5FFFh		 E_4000h
E_4FFFh		 E_3000h
E_3FFFh		 E_2000h
E_2FFFh		 E_1000h
E_2FFFh		 E_0000h
E_0FFFh
 
MTRR_FIX_4K_E8000
 
0000_026Dh		 E_F000h
E_FFFFh		 E_E000h
E_EFFFh		 E_D000h
E_DFFFh		 E_C000h
E_CFFFh		 E_B000h
E_BFFFh		 E_A000h
E_AFFFh		 E_9000h
E_9FFFh		 E_8000h
E_8FFFh
 
MTRR_FIX_4K_F0000
 
0000_026Eh		 F_7000h
F_7FFFh		 F_6000h
F_6FFFh		 F_5000h
F_5FFFh		 F_4000h
F_4FFFh		 F_3000h
F_3FFFh		 F_2000h
F_2FFFh		 F_1000h
F_2FFFh		 F_0000h
F_0FFFh
 
MTRR_FIX_4K_F8000
 
0000_026Fh		 F_F000h
F_FFFFh		 F_E000h
F_EFFFh		 F_D000h
F_DFFFh		 F_C000h
F_CFFFh		 F_B000h
F_BFFFh		 F_A000h
F_AFFFh		 F_9000h
F_9FFFh		 F_8000h
F_8FFFh

 
Variable Range MTRRs
 
name 6
3		 6
2		 6
1		 6
0		 5
9		 5
8		 5
7		 5
6		 5
5		 5
4		 5
3		 5
2		 5
1		 5
0		 4
9		 4
8		 4
7		 4
6		 4
5		 4
4		 4
3		 4
2		 4
1		 4
0		 3
9		 3
8		 3
7		 3
6		 3
5		 3
4		 3
3		 3
2
3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
MTRR_PHYS_BASE_n
 
0000_0200h
0000_0202h
...		 reserved BASE #1  
BASE
 
 
BASE
 		 res. TYPE
MTRR_PHYS_MASK_n
 
0000_0201h
0000_0203h
...		 reserved MASK #1  
MASK
 
 
MASK
 		 V reserved
note description
#1 The number of actually implemented bits depends on the number of physical address bits.
The remaining bits are reserved if less than 52 physical address bits are implemented.

 
SMRRs
 
name 6
3		 6
2		 6
1		 6
0		 5
9		 5
8		 5
7		 5
6		 5
5		 5
4		 5
3		 5
2		 5
1		 5
0		 4
9		 4
8		 4
7		 4
6		 4
5		 4
4		 4
3		 4
2		 4
1		 4
0		 3
9		 3
8		 3
7		 3
6		 3
5		 3
4		 3
3		 3
2
3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
SMRR_PHYS_BASE
 
0000_01F2h		  
reserved
 
 
BASE
 		 res. TYPE
SMRR_PHYS_MASK
 
0000_01F3h		  
reserved
 
 
MASK
 		 V reserved


 
Machine Check Exception
 
name 3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
 
MCAR
 
0000_0000h		  
ADDR
 
 
MCTR
 
0000_0001h		 reserved or used otherwise L
C
K		 M
I
O		 D
C		 W
R		 C
H
K

 
Machine Check Architecture
 
name 6
3		 6
2		 6
1		 6
0		 5
9		 5
8		 5
7		 5
6		 5
5		 5
4		 5
3		 5
2		 5
1		 5
0		 4
9		 4
8		 4
7		 4
6		 4
5		 4
4		 4
3		 4
2		 4
1		 4
0		 3
9		 3
8		 3
7		 3
6		 3
5		 3
4		 3
3		 3
2
3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
MCG_CONTAIN
 
0000_0178h		  
reserved
 
 
reserved
 		 V
EN		 P
EN
MCG_CAP
 
0000_0179h		  
reserved
 
reserved LM
CE
P		 EL
OG
P		 E
M
C
P		 S
E
R
P		 EXT_COUNT reserved T
E
S
P		 CM
CI
P		 E
X
T
P		 C
T
L
P		  
COUNT (n)
 
MCG_STATUS
 
0000_017Ah		  
reserved
 
 
reserved
 		 LM
CE
S		 M
C
I
P		 E
I
P
V		 R
I
P
V
MCG_CTL
 
0000_017Bh		  
reserved
 
 
reserved
 
MCG_EXT_CTL
 
0000_04D0h		  
reserved
 
 
reserved
 		 LM
CE
EN

 
MCA Error-Reporting Register Banks
 
name 6
3		 6
2		 6
1		 6
0		 5
9		 5
8		 5
7		 5
6		 5
5		 5
4		 5
3		 5
2		 5
1		 5
0		 4
9		 4
8		 4
7		 4
6		 4
5		 4
4		 4
3		 4
2		 4
1		 4
0		 3
9		 3
8		 3
7		 3
6		 3
5		 3
4		 3
3		 3
2
3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
MCn_CTL2
 
0000_0280h
0000_0281h
...		  
reserved
 
 
r.
 		 CM
CI
EN		 reserved THRESHOLD
MCn_CTL #2
 
0000_0400h
0000_0404h
...		 E
E
6
3		 E
E
6
2		 E
E
6
1		 E
E
6
0		 E
E
5
9		 E
E
5
8		 E
E
5
7		 E
E
5
6		 E
E
5
5		 E
E
5
4		 E
E
5
3		 E
E
5
2		 E
E
5
1		 E
E
5
0		 E
E
4
9		 E
E
4
8		 E
E
4
7		 E
E
4
6		 E
E
4
5		 E
E
4
4		 E
E
4
3		 E
E
4
2		 E
E
4
1		 E
E
4
0		 E
E
3
9		 E
E
3
8		 E
E
3
7		 E
E
3
6		 E
E
3
5		 E
E
3
4		 E
E
3
3		 E
E
3
2
E
E
3
1		 E
E
3
0		 E
E
2
9		 E
E
2
8		 E
E
2
7		 E
E
2
6		 E
E
2
5		 E
E
2
4		 E
E
2
3		 E
E
2
2		 E
E
2
1		 E
E
2
0		 E
E
1
9		 E
E
1
8		 E
E
1
7		 E
E
1
6		 E
E
1
5		 E
E
1
4		 E
E
1
3		 E
E
1
2		 E
E
1
1		 E
E
1
0		 E
E
0
9		 E
E
0
8		 E
E
0
7		 E
E
0
6		 E
E
0
5		 E
E
0
4		 E
E
0
3		 E
E
0
2		 E
E
0
1		 E
E
0
0
MCn_STATUS
 
0000_0401h
0000_0405h
...		 V
A
L		 O U
C		 E
N		 MI
SC
V		 AD
DR
V		 P
C
C		 OTHER
S AR TES CORRECTED ERROR COUNT FW OTHER
 
ERROR_MS
 		 ERROR_MCA
MCn_ADDR
 
0000_0402h
0000_0406h
...		 ADDR #1 ADDR #1  
ADDR #1
 
 
ADDR #1
 
MCn_MISC
 
0000_0403h
0000_0407h
...		  
reserved
 
 
reserved
 
notes descriptions
#1 Depending on the particular error, the address can be virtual or physical.
#2 Intel P6-core processors alias MC0_CTL to EBL_CR_POWERON.

 
MCA Extended State Registers
 
name 6
3		   0
 
MCG_rAX
 
0000_0180h		  
rAX
 
 
MCG_rBX
 
0000_0181h		  
rBX
 
 
MCG_rCX
 
0000_0182h		  
rCX
 
 
MCG_rDX
 
0000_0183h		  
rDX
 
 
MCG_rSI
 
0000_0184h		  
rSI
 
 
MCG_rDI
 
0000_0185h		  
rDI
 
 
MCG_rBP
 
0000_0186h		  
rBP
 
 
MCG_rSP
 
0000_0187h		  
rSP
 
 
MCG_rFLAGS
 
0000_0188h		  
rFLAGS
 
 
MCG_rIP
 
0000_0189h		  
rIP
 
 
MCG_MISC
 
0000_018Ah		  
reserved
 		 D
S
MCG_RESx
 
0000_018Bh
0000_018Ch
...		  
processor-specific information (optional)
 
 
processor-specific information (optional)
 
 
MCG_R8
 
0000_0190h		  
R8
 
 
MCG_R9
 
0000_0191h		  
R9
 
 
MCG_R10
 
0000_0192h		  
R10
 
 
MCG_R11
 
0000_0193h		  
R11
 
 
MCG_R12
 
0000_0194h		  
R12
 
 
MCG_R13
 
0000_0195h		  
R13
 
 
MCG_R14
 
0000_0196h		  
R14
 
 
MCG_R15
 
0000_0197h		  
R15
 


 
Local APIC
 
name 6
3		 6
2		 6
1		 6
0		 5
9		 5
8		 5
7		 5
6		 5
5		 5
4		 5
3		 5
2		 5
1		 5
0		 4
9		 4
8		 4
7		 4
6		 4
5		 4
4		 4
3		 4
2		 4
1		 4
0		 3
9		 3
8		 3
7		 3
6		 3
5		 3
4		 3
3		 3
2
3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
APIC_BASE
 
0000_001Bh		  
reserved
 		  
APIC base #1
 		 APIC
base
APIC base E E
X
T
D		 i
g
n		 B
S
P		 reserved
note description
#1 The number of actually implemented bits depends on the number of physical address bits.
The remaining bits are reserved if less than 52 physical address bits are implemented.


 
BNDCFGS
 
name 6
3		 6
2		 6
1		 6
0		 5
9		 5
8		 5
7		 5
6		 5
5		 5
4		 5
3		 5
2		 5
1		 5
0		 4
9		 4
8		 4
7		 4
6		 4
5		 4
4		 4
3		 4
2		 4
1		 4
0		 3
9		 3
8		 3
7		 3
6		 3
5		 3
4		 3
3		 3
2
3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
BNDCFGS
 
0000_0D90h		  
BD base
 
 
BD base
 		 reserved B
p
r
v		 En


 
PASID
 
name 6
3		 6
2		 6
1		 6
0		 5
9		 5
8		 5
7		 5
6		 5
5		 5
4		 5
3		 5
2		 5
1		 5
0		 4
9		 4
8		 4
7		 4
6		 4
5		 4
4		 4
3		 4
2		 4
1		 4
0		 3
9		 3
8		 3
7		 3
6		 3
5		 3
4		 3
3		 3
2
3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
PASID
 
0000_0D93h		  
reserved
 
 
V
 		 reserved PASID for ENQCMD


 
XSS
 
name 6
3		 6
2		 6
1		 6
0		 5
9		 5
8		 5
7		 5
6		 5
5		 5
4		 5
3		 5
2		 5
1		 5
0		 4
9		 4
8		 4
7		 4
6		 4
5		 4
4		 4
3		 4
2		 4
1		 4
0		 3
9		 3
8		 3
7		 3
6		 3
5		 3
4		 3
3		 3
2
3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
XSS
 
0000_0DA0h		 r
e
s		 L
W
P		 reserved
reserved XT
D
A
T		 XT
C
F
G		 H
W
P		 A
L
B
R		 U
IN
TR		 H
D
C		 C
E
T
S		 C
E
T
U		 EN
QC
MD		 P
K
R
U		 T
P
C
S		 V
16
...
31		 V
5
1
2		 K
r
e
g		 BN
DC
SR		 B
r
e
g		 Y
M
M		 X
M
M		 X
8
7


note: The following SMM related registers are visible in the SMM state save map.
 
SMM related internal registers
 
name 6
3		   3
2		 3
1		   0
SMBASE  
SMM base address
 
IO
RESTART
RIP		  
RIP of most recent IN/OUT instruction (for I/O restart on RSM)
 
IO
RESTART
RCX		  
RCX of most recent IN/OUT instruction (for I/O restart on RSM)
 
IO
RESTART
RSI		  
RSI of most recent IN/OUT instruction (for I/O restart on RSM)
 
IO
RESTART
RDI		  
RDI of most recent IN/OUT instruction (for I/O restart on RSM)
 


note: Some of the following additional internal flags are visible in the SMM state save map.
 
additional internal flags
 
name description
TEMP_DR6 used to collect breakpoint information for DR6.B?
CAUSING_DB used to indicate that the CPU is in the process of generating a #DB exception
BLOCK_INIT set by SMI, cleared by IRET/RSM instruction or RESET
BLOCK_SMI set by SMI, cleared by RSM instruction or RESET/INIT
BLOCK_NMI set by SMI/NMI, cleared by IRET instruction or RESET/INIT
LATCH_INIT one INIT can be latched while INITs are blocked
LATCH_SMI one SMI can be latched while SMIs are blocked
LATCH_NMI one NMI can be latched while NMIs are blocked
IN_REP used to suppress fetch and decode in subsequent REP string instruction iterations
IN_SMM set by SMI, cleared by RSM instruction or RESET/INIT
IN_HLT set by HLT instruction, optionally set by RSM instruction,
cleared by RESET/INIT/SMI/NMI/INTR
IN_SHUTDOWN set by triple fault, cleared by RESET/INIT/SMI/NMI
IN_FP_FREEZE set by waiting FP instruction if unmasked pending FP exception while CR0.NE=0
and IGNNE#=deasserted, cleared by RESET/INIT/SMI/NMI/INTR
SUPPRESS_INTERRUPTS used to implement external interrupt suppression


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