x86 architecture
paging


 
page size and used paging structures (2-level and 3-level)
 
CR0.PG CR4.PAE CR4.PSE PDE.PS physical
address
size		 page size CR3
points
to		 PDPT PD PT
 
0
 		 x x x 32-bit --- --- --- --- ---
1 0 0 x 32-bit 4KB PD --- 1024
PDEs
(32-bit)		 1024
PTEs
(32-bit)
1 0 1 0 32-bit 4KB PD --- 1024
PDEs
(32-bit)		 1024
PTEs
(32-bit)
1 0 1 1 32-bit
or
36-bit		 4MB PD --- 1024
PDEs
(32-bit)		 1024
PTEs
(32-bit)
1 1 x 0 36-bit 4KB PDPT 4
PDPTEs
(64-bit)		 512
PDEs
(64-bit)		 512
PTEs
(64-bit)
1 1 x 1 36-bit 2MB PDPT 4
PDPTEs
(64-bit)		 512
PDEs
(64-bit)		 512
PTEs
(64-bit)

 
page size and used paging structures (4-level)
 
CR0.PG CR4.PAE CR4.PSE PS in
PMLxE		 page size CR3
points
to		 PML4 PML3 PML2 PML1
1 1 x 3=1 1GB PML4 512
PML4Es
(64-bit)		 512
PML3Es
(64-bit)		 512
PML2Es
(64-bit)		 512
PML1Es
(64-bit)
1 1 x 2=1 2MB PML4 512
PML4Es
(64-bit)		 512
PML3Es
(64-bit)		 512
PML2Es
(64-bit)		 512
PML1Es
(64-bit)
1 1 x 2=0 4KB PML4 512
PML4Es
(64-bit)		 512
PML3Es
(64-bit)		 512
PML2Es
(64-bit)		 512
PML1Es
(64-bit)
note The number of table levels depends on the number of implemented virtual address bits.
The first implementation supports four levels, to handle 9+9+9+9+12 = 48 virtual address bits.
Five or six levels would be required for up to 57 or 64 virtual address bits, respectively.


 
virtual address translation (2-level and 3-level)
 
P
S		 P
A
E		   3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
4
K
B		 0 PDE # PTE # offset
4
M
B		 PDE # offset
4
K
B		 1 PDP-
TE #		 PDE # PTE # offset
2
M
B		 PDP-
TE #		 PDE # offset

 
virtual address translation (4-level)
 
P
S		   6
3		   5
7		 5
6		   4
8		 4
7		   3
9		 3
8		   3
0		 2
9		   2
1		 2
0		   1
2		 1
1		   0
4
K
B		 must be canonical
(i.e. sign-extended)		 PML4E # PML3E # PML2E # PML1E # offset
2
M
B		 must be canonical
(i.e. sign-extended)		 PML4E # PML3E # PML2E # offset
1
G
B		 must be canonical
(i.e. sign-extended)		 PML4E # PML3E # offset


 
2-level 4KB/4MB paging structures
 
entry 3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
4KB
PDE		 page table base AVL G 0 D A P
C
D		 P
W
T		 U
/
S		 W
/
R		 P
4MB
PDE		 page base reserved P
A
T		 AVL G 1 D A P
C
D		 P
W
T		 U
/
S		 W
/
R		 P
page base (low) p.b. (high) #1 p. b. (high)
4KB
PTE		 page base AVL G P
A
T		 D A P
C
D		 P
W
T		 U
/
S		 W
/
R		 P
note description
#1 The number of actually implemented bits depends on the number of physical address bits.
The remaining bits are reserved if less than 41 physical address bits are implemented.

 
3-level 4KB/2MB paging structures
 
entry 6
3		 6
2		 6
1		 6
0		 5
9		 5
8		 5
7		 5
6		 5
5		 5
4		 5
3		 5
2		 5
1		 5
0		 4
9		 4
8		 4
7		 4
6		 4
5		 4
4		 4
3		 4
2		 4
1		 4
0		 3
9		 3
8		 3
7		 3
6		 3
5		 3
4		 3
3		 3
2
3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
PDPTE reserved  
page directory base #1
 		 page
directory
base
page directory base AVL res. P
C
D		 P
W
T		 res. P
4KB
PDE		 N
X		 reserved  
page table base #1
 		 page
table
base
page table base AVL G 0 D A P
C
D		 P
W
T		 U
/
S		 W
/
R		 P
2MB
PDE		 N
X		 reserved  
page base #1
 		 page
base
page base reserved P
A
T		 AVL G 1 D A P
C
D		 P
W
T		 U
/
S		 W
/
R		 P
4KB
PTE		 N
X		 reserved  
page base #1
 		 page
base
page base AVL G P
A
T		 D A P
C
D		 P
W
T		 U
/
S		 W
/
R		 P
note description
#1 The number of actually implemented bits depends on the number of physical address bits.
The remaining bits are reserved if less than 52 physical address bits are implemented.

 
4-level 4KB/2MB paging structures
 
entry 6
3		 6
2		 6
1		 6
0		 5
9		 5
8		 5
7		 5
6		 5
5		 5
4		 5
3		 5
2		 5
1		 5
0		 4
9		 4
8		 4
7		 4
6		 4
5		 4
4		 4
3		 4
2		 4
1		 4
0		 3
9		 3
8		 3
7		 3
6		 3
5		 3
4		 3
3		 3
2
3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
PML4E
for
PML3		 N
X		  
AVL
 		  
PML3 base #1
 		 PML3
base
PML3 base AVL res. D A P
C
D		 P
W
T		 U
/
S		 W
/
R		 P
PML3E
for
PML2		 N
X		  
AVL
 		  
PML2 base #1
 		 PML2
base
PML2 base AVL G 0 D A P
C
D		 P
W
T		 U
/
S		 W
/
R		 P
PML2E
for
PML1		 N
X		  
AVL
 		  
PML1 base #1
 		 PML1
base
PML1 base AVL G 0 D A P
C
D		 P
W
T		 U
/
S		 W
/
R		 P
PML3E
for
1GB
page		 N
X		  
AVL
 		  
page base #1
 		 page
base
p. b. reserved P
A
T		 AVL G 1 D A P
C
D		 P
W
T		 U
/
S		 W
/
R		 P
PML2E
for
2MB
page		 N
X		  
AVL
 		  
page base #1
 		 page
base
page base reserved P
A
T		 AVL G 1 D A P
C
D		 P
W
T		 U
/
S		 W
/
R		 P
PML1E
for
4KB
page		 N
X		  
AVL
 		  
page base #1
 		 page
base
page base AVL G P
A
T		 D A P
C
D		 P
W
T		 U
/
S		 W
/
R		 P
note description
#1 The number of actually implemented bits depends on the number of physical address bits.
The remaining bits are reserved if less than 52 physical address bits are implemented.


 
#PF exception error code
 
1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
reserved I
/
D		 R
S
V		 U
/
S		 W
/
R		 P


main page