x86 architecture
2 byte opcodes




note: A leading bold V indicates that the instruction can be VEX-encoded, in which case it may have additional operands.
note: A leading bold ! indicates that the 256-bit version was only introduced with AVX2 and that it can only be VEX-encoded.



pre-
fix
0Fh
xxh
 
x0h
 
x1h x2h x3h x4h x5h x6h x7h
 
n/a
 
0xh group #6 group #7 LAR
Gv,Ew
LSL
Gv,Ew
LOADALL?
RESET?
HANG?
(80286)
LOADALL
(80286)
SYSCALL
(see CPUID)
CLTS LOADALL
(80386)
SYSRET
(see CPUID)
 
n/a
 
1xh UMOV
Eb,Gb
(80386/486)
UMOV
Ev,Gv
(80386/486)
UMOV
Gb,Eb
(80386/486)
UMOV
Gv,Ev
(80386/486)
 
n/a
 
VMOVUPS
Vx,Wx
(SSE)
VMOVUPS
Wx,Vx
(SSE)
VMOVLPS
Vo,Ho,Mo.q (SSE)
VMOVHLPS #1
Vo,Ho,Uo (SSE)
VMOVLPS
Mo.q,Vo (SSE)
 
 
VUNPCKLPS
Vx,Hx,Wx
(SSE) #3
VUNPCKHPS
Vx,Hx,Wx
(SSE)
VMOVHPS
Vo,Ho,Mo.q (SSE)
VMOVLHPS #1
Vo,Ho,Uo (SSE)
VMOVHPS
Mo.q,Vo (SSE)
 
 
 
66h
 
VMOVUPD
Vx,Wx
(SSE2)
VMOVUPD
Wx,Vx
(SSE2)
VMOVLPD
Vo,Ho,Mo.q (SSE2)
 
 
VMOVLPD
Mo.q,Vo (SSE2)
 
 
VUNPCKLPD
Vx,Hx,Wx
(SSE2) #3
VUNPCKHPD
Vx,Hx,Wx
(SSE2)
VMOVHPD
Vo,Ho,Mo.q (SSE2)
 
 
VMOVHPD
Mo.q,Vo (SSE2)
 
 
 
F3h
 
VMOVSS
Vo,Mo.d (SSE)
VMOVSS
Vo,Ho,Uo (SSE)
VMOVSS
Mo.d,Vo (SSE)
VMOVSS
Uo,Ho,Vo (SSE)
VMOVSLDUP
Vx,Wx
(SSE3)
VMOVSHDUP
Vx,Wx
(SSE3)
 
F2h
 
VMOVSD
Vo,Mo.q (SSE2)
VMOVSD
Vo,Ho,Uo (SSE2)
VMOVSD
Mo.q,Vo (SSE2)
VMOVSD
Uo,Ho,Vo (SSE2)
VMOVDDUP
Vo,Wo.q
Vy,Wy
(SSE3)
E  +
V  n
E  /
X  a
VMOVUPS
Vn {K} {z},
Wn (W=0)

(AVX512F,VL)
VMOVUPS
Wn {K} {z},
Vn (W=0)

(AVX512F,VL)
VMOVLPS
Vo,Ho,Mo.q (W=0)
VMOVHLPS
Vo,Ho,Uo (W=0)
(AVX512F)
VMOVLPS
Mo.q,Vo (W=0)
 
 
(AVX512F)
VUNPCKLPS
Vn {K} {z},Hn,
B32 (Wn) (W=0) #3

(AVX512F,VL)
VUNPCKHPS
Vn {K} {z},Hn,
B32 (Wn) (W=0)

(AVX512F,VL)
VMOVHPS
Vo,Ho,Mo.q (W=0)
VMOVLHPS
Vo,Ho,Uo (W=0)
(AVX512F)
VMOVHPS
Mo.q,Vo (W=0)
 
 
(AVX512F)
E  +
V  6
E  6
X  h
VMOVUPD
Vn {K} {z},
Wn (W=1)

(AVX512F,VL)
VMOVUPD
Wn {K} {z},
Vn (W=1)

(AVX512F,VL)
VMOVLPD
Vo,Ho,Mo.q (W=1)
 
 
(AVX512F)
VMOVLPD
Mo.q,Vo (W=1)
 
 
(AVX512F)
VUNPCKLPD
Vn {K} {z},Hn,
B64 (Wn) (W=1) #3

(AVX512F,VL)
VUNPCKHPD
Vn {K} {z},Hn,
B64 (Wn) (W=1)

(AVX512F,VL)
VMOVHPD
Vo,Ho,Mo.q (W=1)
 
 
(AVX512F)
VMOVHPD
Mo.q,Vo (W=1)
 
 
(AVX512F)
E  +
V  F
E  3
X  h
VMOVSS
Vo {K} {z},Mo.d (W=0)
VMOVSS
Vo {K} {z},Ho,Uo (0)
(AVX512F)
VMOVSS
Mo.d {K},Vo (W=0)
VMOVSS
Uo {K} {z},Ho,Vo (0)
(AVX512F)
VMOVSLDUP
Vn {K} {z},
Wn (W=0)

(AVX512F,VL)
VMOVSHDUP
Vn {K} {z},
Wn (W=0)

(AVX512F,VL)
E  +
V  F
E  2
X  h
VMOVSD
Vo {K} {z},Mo.q (W=1)
VMOVSD
Vo {K} {z},Ho,Uo (1)
(AVX512F)
VMOVSD
Mo.q {K},Vo (W=1)
VMOVSD
Uo {K} {z},Ho,Vo (1)
(AVX512F)
VMOVDDUP
Vo {K} {z},Wo.q (1)
Vy {K} {z},Wy (1)
Vz {K} {z},Wz (1)

(AVX512F,VL)
 
n/a
 
2xh SSE5A
(AMD)
SSE5A
(AMD)
 
n/a
 
MOV#mod, F64
Ry,Cy
(80386+)
MOV#mod, F64
Ry,Dy
(80386+)
MOV#mod, F64
Cy,Ry
(80386+)
MOV#mod, F64
Dy,Ry
(80386+)
MOV#mod, F64
Ry,Ty
(80386/486)
MOV#mod, F64
Ty,Ry
(80386/486)
 
F0h
 
MOV#mod
Rd,CR8D
(see CPUID)
MOV#mod
CR8D,Rd
(see CPUID)
 
n/a
 
3xh WRMSR
(see CPUID)
RDTSC
(see CPUID)
RDMSR
(see CPUID)
RDPMC
(P55 and P6+)
SYSENTER
(see CPUID)
(LM: Intel-only)
SYSEXIT
(see CPUID)
(LM: Intel-only)
GETSEC
(see CPUID)
 
n/a
 
RDSHR#reg
Ed
(Cyrix)
WRSHR#reg
Ed
(Cyrix)
 
n/a
 
4xh CMOVO
Gv,Ev
(see CPUID)
CMOVNO
Gv,Ev
(see CPUID)
CMOVB
Gv,Ev
(see CPUID)
CMOVNB
Gv,Ev
(see CPUID)
CMOVZ
Gv,Ev
(see CPUID)
CMOVNZ
Gv,Ev
(see CPUID)
CMOVBE
Gv,Ev
(see CPUID)
CMOVNBE
Gv,Ev
(see CPUID)
VEX
n/a
 
 
KAND
rKw,mKw (K1OM)
 
 
KANDN
rKw,mKw (K1OM)
 
 
KANDNR
rKw,mKw (K1OM)
 
 
KNOT
rKw,mKw (K1OM)
 
 
KOR
rKw,mKw (K1OM)
 
 
KXNOR
rKw,mKw (K1OM)
 
 
KXOR
rKw,mKw (K1OM)
VEX
66h
W0
 
 
 
KANDB
rK,vK,mK (L=1)
(AVX512DQ)
 
 
 
KANDNB
rK,vK,mK (L=1)
(AVX512DQ)
 
 
 
KNOTB
rK,mK (L=0)
(AVX512DQ)
 
 
 
KORB
rK,vK,mK (L=1)
(AVX512DQ)
 
 
 
KXNORB
rK,vK,mK (L=1)
(AVX512DQ)
 
 
 
KXORB
rK,vK,mK (L=1)
(AVX512DQ)
VEX
n/a
W0
 
 
 
KANDW
rK,vK,mK (L=1)
(AVX512F)
 
 
 
KANDNW
rK,vK,mK (L=1)
(AVX512F)
 
 
 
KNOTW
rK,mK (L=0)
(AVX512F)
 
 
 
KORW
rK,vK,mK (L=1)
(AVX512F)
 
 
 
KXNORW
rK,vK,mK (L=1)
(AVX512F)
 
 
 
KXORW
rK,vK,mK (L=1)
(AVX512F)
VEX
66h
W1
 
 
 
KANDD
rK,vK,mK (L=1)
(AVX512BW)
 
 
 
KANDND
rK,vK,mK (L=1)
(AVX512BW)
 
 
 
KNOTD
rK,mK (L=0)
(AVX512BW)
 
 
 
KORD
rK,vK,mK (L=1)
(AVX512BW)
 
 
 
KXNORD
rK,vK,mK (L=1)
(AVX512BW)
 
 
 
KXORD
rK,vK,mK (L=1)
(AVX512BW)
VEX
n/a
W1
 
 
 
KANDQ
rK,vK,mK (L=1)
(AVX512BW)
 
 
 
KANDNQ
rK,vK,mK (L=1)
(AVX512BW)
 
 
 
KNOTQ
rK,mK (L=0)
(AVX512BW)
 
 
 
KORQ
rK,vK,mK (L=1)
(AVX512BW)
 
 
 
KXNORQ
rK,vK,mK (L=1)
(AVX512BW)
 
 
 
KXORQ
rK,vK,mK (L=1)
(AVX512BW)
 
n/a
 
5xh  
 
VMOVMSKPS
Gy,Ux (SSE)
VSQRTPS
Vx,Wx
(SSE)
VRSQRTPS
Vx,Wx
(SSE)
VRCPPS
Vx,Wx
(SSE)
VANDPS
Vx,Hx,Wx
(SSE)
VANDNPS
Vx,Hx,Wx
(SSE)
VORPS
Vx,Hx,Wx
(SSE)
VXORPS
Vx,Hx,Wx
(SSE)
 
66h
 
 
 
VMOVMSKPD
Gy,Ux (SSE2)
VSQRTPD
Vx,Wx
(SSE2)
VANDPD
Vx,Hx,Wx
(SSE2)
VANDNPD
Vx,Hx,Wx
(SSE2)
VORPD
Vx,Hx,Wx
(SSE2)
VXORPD
Vx,Hx,Wx
(SSE2)
 
F3h
 
VSQRTSS
Vo,Ho,Wo.d
(SSE)
VRSQRTSS
Vo,Ho,Wo.d
(SSE)
VRCPSS
Vo,Ho,Wo.d
(SSE)
 
F2h
 
VSQRTSD
Vo,Ho,Wo.q
(SSE2)
E  +
V  n
E  /
X  a
VSQRTPS
Vn {K} {z},
B32 (Wn) {er} (W=0)

(AVX512F,VL)
VANDPS
Vn {K} {z},Hn,
B32 (Wn) (W=0)

(AVX512DQ,VL)
VANDNPS
Vn {K} {z},Hn,
B32 (Wn) (W=0)

(AVX512DQ,VL)
VORPS
Vn {K} {z},Hn,
B32 (Wn) (W=0)

(AVX512DQ,VL)
VXORPS
Vn {K} {z},Hn,
B32 (Wn) (W=0)

(AVX512DQ,VL)
E  +
V  6
E  6
X  h
VSQRTPD
Vn {K} {z},
B64 (Wn) {er} (W=1)

(AVX512F,VL)
VANDPD
Vn {K} {z},Hn,
B64 (Wn) (W=1)

(AVX512DQ,VL)
VANDNPD
Vn {K} {z},Hn,
B64 (Wn) (W=1)

(AVX512DQ,VL)
VORPD
Vn {K} {z},Hn,
B64 (Wn) (W=1)

(AVX512DQ,VL)
VXORPD
Vn {K} {z},Hn,
B64 (Wn) (W=1)

(AVX512DQ,VL)
E  +
V  F
E  3
X  h
VSQRTSS
Vo {K} {z},Ho,
Wo.d {er} (W=0)

(AVX512F)
E  +
V  F
E  2
X  h
VSQRTSD
Vo {K} {z},Ho,
Wo.q {er} (W=1)

(AVX512F)
 
n/a
 
6xh PUNPCKLBW
Pq,Qd
(MMX)
PUNPCKLWD
Pq,Qd
(MMX)
PUNPCKLDQ
Pq,Qd
(MMX)
PACKSSWB
Pq,Qq
(MMX)
PCMPGTB
Pq,Qq
(MMX)
PCMPGTW
Pq,Qq
(MMX)
PCMPGTD
Pq,Qq
(MMX)
PACKUSWB
Pq,Qq
(MMX)
 
66h
 
!VPUNPCKLBW
Vx,Hx,Wx
(SSE2) #3
!VPUNPCKLWD
Vx,Hx,Wx
(SSE2) #3
!VPUNPCKLDQ
Vx,Hx,Wx
(SSE2) #3
!VPACKSSWB
Vx,Hx,Wx
(SSE2)
!VPCMPGTB
Vx,Hx,Wx
(SSE2)
!VPCMPGTW
Vx,Hx,Wx
(SSE2)
!VPCMPGTD
Vx,Hx,Wx
(SSE2)
!VPACKUSWB
Vx,Hx,Wx
(SSE2)
M  +
V  6
E  6
X  h
VPCMPGTD
rKw {Kw},Hz,
Si32r (Wzt) (W=0)

(K1OM)
E  +
V  6
E  6
X  h
VPUNPCKLBW
Vn {K} {z},Hn,
Wn (W=x) #3

(AVX512BW,VL)
VPUNPCKLWD
Vn {K} {z},Hn,
Wn (W=x) #3

(AVX512BW,VL)
VPUNPCKLDQ
Vn {K} {z},Hn,
B32 (Wn) (W=0) #3

(AVX512F,VL)
VPACKSSWB
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPCMPGTB
rK {K},Hn,
Wn (W=x)

(AVX512BW,VL)
VPCMPGTW
rK {K},Hn,
Wn (W=x)

(AVX512BW,VL)
VPCMPGTD
rK {K},Hn,
B32 (Wn) (W=0)

(AVX512F,VL)
VPACKUSWB
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
 
n/a
 
7xh PSHUFW
Pq,Qq,Ib
(MMX-SSE)
group #12
PSHIMW
(MMX)
group #13
PSHIMD
(MMX)
group #14
PSHIMQ
(MMX)
PCMPEQB
Pq,Qq
(MMX)
PCMPEQW
Pq,Qq
(MMX)
PCMPEQD
Pq,Qq
(MMX)
EMMS (MMX)
VZEROUPPER (0)
VZEROALL (L=1)
(AVX)
 
66h
 
!VPSHUFD
Vx,Wx,Ib
(SSE2)
group #12
!VPSHIMW
(SSE2)
group #13
!VPSHIMD
(SSE2)
group #14
!VPSHIMQ/DQ
(SSE2)
!VPCMPEQB
Vx,Hx,Wx
(SSE2)
!VPCMPEQW
Vx,Hx,Wx
(SSE2)
!VPCMPEQD
Vx,Hx,Wx
(SSE2)
 
F3h
 
!VPSHUFHW
Vx,Wx,Ib
(SSE2)
group #12 group #13 group #14
 
F2h
 
!VPSHUFLW
Vx,Wx,Ib
(SSE2)
group #12 group #13 group #14
M  +
V  6
E  6
X  h
VPSHUFD
Vz {Kw},
Si64n (Wzt),Ib (W=0)

(K1OM)
group #13
VPSHIMD
(K1OM)
VPCMPEQD
rKw {Kw},Hz,
Si32r (Wzt) (W=0)

(K1OM)
E  +
V  6
E  6
X  h
VPSHUFD
Vn {K} {z},
B32 (Wn),Ib (W=0)

(AVX512F,VL)
group #12
VPSHIMW
(AVX512BW,VL)
group #13
VPSHIMD
(AVX512F,VL)
group #14
VPSHIMQ
(AVX512F,VL)
VPSHIMDQ
(AVX512BW,VL)
VPCMPEQB
rK {K},Hn,
Wn (W=x)

(AVX512BW,VL)
VPCMPEQW
rK {K},Hn,
Wn (W=x)

(AVX512BW,VL)
VPCMPEQD
rK {K},Hn,
B32 (Wn) (W=0)

(AVX512F,VL)
E  +
V  F
E  3
X  h
VPSHUFHW
Vn {K} {z},
Wn,Ib (W=x)

(AVX512BW,VL)
E  +
V  F
E  2
X  h
VPSHUFLW
Vn {K} {z},
Wn,Ib (W=x)

(AVX512BW,VL)
 
n/a
 
8xh JODf64
Jz
(80386+)
JNODf64
Jz
(80386+)
JBDf64
Jz
(80386+)
JNBDf64
Jz
(80386+)
JZDf64
Jz
(80386+)
JNZDf64
Jz
(80386+)
JBEDf64
Jz
(80386+)
JNBEDf64
Jz
(80386+)
VEX
n/a
JKZDv64
vKw,Jz
(K1OM)
JKNZDv64
vKw,Jz
(K1OM)
 
n/a
 
9xh SETO#reg
Eb
(80386+)
SETNO#reg
Eb
(80386+)
SETB#reg
Eb
(80386+)
SETNB#reg
Eb
(80386+)
SETZ#reg
Eb
(80386+)
SETNZ#reg
Eb
(80386+)
SETBE#reg
Eb
(80386+)
SETNBE#reg
Eb
(80386+)
VEX
n/a
 
 
KMOV
rKw,mKw (K1OM)
 
 
KMOV
rKw,Ry (K1OM)
 
 
KMOV
Gy,mKw (K1OM)
 
 
KCONCATH
Rq,vKw,mKw (K1OM)
 
 
KCONCATL
Ry,vKw,mKw (K1OM)
VEX
66h
W0
KMOVB
rK,Mb (L=0)
(AVX512DQ)
KMOVB
rK,mK (L=0)
(AVX512DQ)
KMOVB
Mb,rK (L=0)
(AVX512DQ)
 
 
 
 
 
 
KMOVB
rK,Ry (L=0)
(AVX512DQ)
 
 
 
KMOVB
Gy,mK (L=0)
(AVX512DQ)
VEX
n/a
W0
KMOVW
rK,Mw (L=0)
(AVX512F)
KMOVW
rK,mK (L=0)
(AVX512F)
KMOVW
Mw,rK (L=0)
(AVX512F)
 
 
 
 
 
 
KMOVW
rK,Ry (L=0)
(AVX512F)
 
 
 
KMOVW
Gy,mK (L=0)
(AVX512F)
VEX
66h
W1
KMOVD
rK,Md (L=0)
(AVX512BW)
KMOVD
rK,mK (L=0)
(AVX512BW)
KMOVD
Md,rK (L=0)
(AVX512BW)
 
 
 
VEX
n/a
W1
KMOVQ
rK,Mq (L=0)
(AVX512BW)
KMOVQ
rK,mK (L=0)
(AVX512BW)
KMOVQ
Mq,rK (L=0)
(AVX512BW)
 
 
 
VEX
F2
W0
 
 
 
KMOVD
rK,Ry (L=0)
(AVX512BW)
 
 
 
KMOVD
Gy,mK (L=0)
(AVX512BW)
VEX
F2
W1
 
 
 
KMOVQ
rK,Rq (L=0)
(AVX512BW)
 
 
 
KMOVQ
Gq,mK (L=0)
(AVX512BW)
 
n/a
 
Axh XBTS and
CMPXCHG
(386/486-A)
IBTS and
CMPXCHG
(386/486-A)
 
n/a
 
PUSHD64
FS
(80386+)
POPD64
FS
(80386+)
CPUID
(EFLAGS.ID)
BT
Ev,Gv
(80386+)
SHLD
Ev,Gv,Ib
(80386+)
SHLD
Ev,Gv,CL
(80386+)
MONTMUL
(Centaur MM)
XSHA
(Centaur HE)
XSTORE
(Centaur RNG)
XCRYPT
(Centaur ACE)
 
n/a
 
Bxh CMPXCHG
Eb,Gb
(80486-B+)
CMPXCHG
Ev,Gv
(80486-B+)
LSS Gv,Mp (w:v)
(80386+)
 
 
BTR
Ev,Gv
(80386+)
LFS Gv,Mp (w:v)
(80386+)
 
 
LGS Gv,Mp (w:v)
(80386+)
 
 
MOVZX
Gv,Eb
(80386+)
MOVZX
Gv,Ew
(80386+)
 
n/a
 
Cxh XADD
Eb,Gb
(80486+)
XADD
Ev,Gv
(80486+)
VCMPccPS #2
Vx,Hx,Wx,Ib
(SSE)
MOVNTI My,Gy
(SSE2-MEM)
 
 
PINSRW
Pq,Mw,Ib
Pq,Rv,Ib
(MMX-SSE)
 
 
PEXTRW
Gy,Nq,Ib (MMX-SSE)
VSHUFPS
Vx,Hx,Wx,Ib
(SSE)
group #9
 
66h
 
VCMPccPD #2
Vx,Hx,Wx,Ib
(SSE2)
VPINSRW
Vo,Ho,Mw,Ib
Vo,Ho,Rv,Ib
(SSE2)
 
 
VPEXTRW
Gy,Uo,Ib (SSE2)
VSHUFPD
Vx,Hx,Wx,Ib
(SSE2)
 
F3h
 
VCMPccSS #2
Vo,Ho,Wo.d,Ib
(SSE)
 
F2h
 
VCMPccSD #2
Vo,Ho,Wo.q,Ib
(SSE2)
M  +
V  n
E  /
X  a
VCMPccPS#2
rKw {Kw},Hz,
Sf32s (Wzt),Ib (W=0)

(K1OM)
M  +
V  6
E  6
X  h
VCMPccPD#2
rKw {Kw},Hz,
Sf64s (Wzt),Ib (W=1)

(K1OM)
E  +
V  n
E  /
X  a
VCMPccPS#2
rK {K},Hn,
B32 (Wn) {sae},Ib (0)

(AVX512F,VL)
VSHUFPS
Vn {K} {z},Hn,
B32 (Wn),Ib (W=0)

(AVX512F,VL)
E  +
V  6
E  6
X  h
VCMPccPD#2
rK {K},Hn,
B64 (Wn) {sae},Ib (1)

(AVX512F,VL)
VPINSRW
Vo,Ho,Mw,Ib
Vo,Ho,Rv,Ib
(AVX512BW)
 
 
VPEXTRW
Gy,Uo,Ib (A512BW)
VSHUFPD
Vn {K} {z},Hn,
B64 (Wn),Ib (W=1)

(AVX512F,VL)
E  +
V  F
E  3
X  h
VCMPccSS#2
rK {K},Ho,
Wo.d {sae},Ib (W=0)

(AVX512F)
E  +
V  F
E  2
X  h
VCMPccSD#2
rK {K},Ho,
Wo.q {sae},Ib (W=1)

(AVX512F)
 
n/a
 
Dxh PSRLW
Pq,Qq
(MMX)
PSRLD
Pq,Qq
(MMX)
PSRLQ
Pq,Qq
(MMX)
PADDQ
Pq,Qq
(MMX-SSE2)
PMULLW
Pq,Qq
(MMX)
 
 
PMOVMSKB
Gy,Nq (MMX-SSE)
 
66h
 
VADDSUBPD
Vx,Hx,Wx
(SSE3)
!VPSRLW
Vx,Hx,Wx
(SSE2) #4
!VPSRLD
Vx,Hx,Wx
(SSE2) #4
!VPSRLQ
Vx,Hx,Wx
(SSE2) #4
!VPADDQ
Vx,Hx,Wx
(SSE2)
!VPMULLW
Vx,Hx,Wx
(SSE2)
VMOVQ
Wo.q,Vo
(SSE2)
 
 
!VPMOVMSKB
Gy,Ux (SSE2)
 
F3h
 
 
 
MOVQ2DQ
Vo,Nq (SSE2-MMX)
 
F2h
 
VADDSUBPS
Vx,Hx,Wx
(SSE3)
 
 
MOVDQ2Q
Pq,Uq (SSE2-MMX)
E  +
V  6
E  6
X  h
VPSRLW
Vn {K} {z},Hn,
Wo.b (W=x)

(AVX512BW,VL)
VPSRLD
Vn {K} {z},Hn,
Wo.b (W=0)

(AVX512F,VL)
VPSRLQ
Vn {K} {z},Hn,
Wo.b (W=1)

(AVX512F,VL)
VPADDQ
Vn {K} {z},Hn,
B64 (Wn) (W=1)

(AVX512F,VL)
VPMULLW
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VMOVQ
Wo.q,
Vo (W=1)

(AVX512F)
 
n/a
 
Exh PAVGB
Pq,Qq
(MMX-SSE)
PSRAW
Pq,Qq
(MMX)
PSRAD
Pq,Qq
(MMX)
PAVGW
Pq,Qq
(MMX-SSE)
PMULHUW
Pq,Qq
(MMX-SSE)
PMULHW
Pq,Qq
(MMX)
MOVNTQ
Mq,Pq (MMX-SSE)
 
 
 
66h
 
!VPAVGB
Vx,Hx,Wx
(SSE2)
!VPSRAW
Vx,Hx,Wx
(SSE2) #4
!VPSRAD
Vx,Hx,Wx
(SSE2) #4
!VPAVGW
Vx,Hx,Wx
(SSE2)
!VPMULHUW
Vx,Hx,Wx
(SSE2)
!VPMULHW
Vx,Hx,Wx
(SSE2)
VCVTTPD2DQ
Vo,Wx
(SSE2)
VMOVNTDQ
Mx,Vx (SSE2)
 
 
 
F3h
 
VCVTDQ2PD
Vo,Wo.q
Vy,Wo
(SSE2)
 
F2h
 
VCVTPD2DQ
Vo,Wx
(SSE2)
M  +
V  F
E  3
X  h
VCVTDQ2PD
Vz {Kw},
Si32c (Wzt.y) (W=0)

(K1OM)
E  +
V  6
E  6
X  h
VPAVGB
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPSRAW
Vn {K} {z},Hn,
Wo.b (W=x)

(AVX512BW,VL)
VPSRAD
Vn {K} {z},Hn,
Wo.b (W=0)

VPSRAQ
Vn {K} {z},Hn,
Wo.b (W=1)

(AVX512F,VL)
VPAVGW
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPMULHUW
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPMULHW
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
 
 
 

VCVTTPD2DQ
Vh {K} {z},
B64 (Wn) {sae} (W=1)

(AVX512F,VL)
VMOVNTDQ
Mn,Vn (W=0)
 
(AVX512F,VL)
 
 
 
 
E  +
V  F
E  3
X  h
VCVTDQ2PD
Vn {K} {z},
B32 (Wh) {er} (W=0)

(AVX512F,VL)
VCVTQQ2PD
Vn {K} {z},
B64 (Wn) {er} (W=1)

(AVX512DQ,VL)
E  +
V  F
E  2
X  h
 
 
 

VCVTPD2DQ
Vh {K} {z},
B64 (Wn) {er} (W=1)

(AVX512F,VL)
 
n/a
 
Fxh PSLLW
Pq,Qq
(MMX)
PSLLD
Pq,Qq
(MMX)
PSLLQ
Pq,Qq
(MMX)
PMULUDQ
Pq,Qq
(MMX-SSE2)
PMADDWD
Pq,Qq
(MMX)
PSADBW
Pq,Qq
(MMX-SSE)
 
 
MASKMOVQ
Pq,Nq (MMX-SSE)
 
66h
 
!VPSLLW
Vx,Hx,Wx
(SSE2) #4
!VPSLLD
Vx,Hx,Wx
(SSE2) #4
!VPSLLQ
Vx,Hx,Wx
(SSE2) #4
!VPMULUDQ
Vx,Hx,Wx
(SSE2)
!VPMADDWD
Vx,Hx,Wx
(SSE2)
!VPSADBW
Vx,Hx,Wx
(SSE2)
 
 
VMASKMOVDQU
Vo,Uo (SSE2)
 
F3h
 
 
F2h
 
VLDDQU
Vx,Mx (SSE3)
 
 
E  +
V  6
E  6
X  h
VPSLLW
Vn {K} {z},Hn,
Wo.b (W=x)

(AVX512BW,VL)
VPSLLD
Vn {K} {z},Hn,
Wo.b (W=0)

(AVX512F,VL)
VPSLLQ
Vn {K} {z},Hn,
Wo.b (W=1)

(AVX512F,VL)
VPMULUDQ
Vn {K} {z},Hn,
B64 (Wn) (W=1)

(AVX512F,VL)
VPMADDWD
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPSADBW
Vn,Hn,
Wn (W=x)

(AVX512BW,VL)

pre-
fix
0Fh
xxh
 
x8h
 
x9h xAh xBh xCh xDh xEh xFh
 
n/a
 
0xh INVD
(80486+)
WBINVD
(80486+)
CL1INVMB
(48-core SCC)
UD1
(80286+)
3DNow! 3DNow! 3DNow!
n/a
66h
F3h
F2h
 
1xh
 
group #16 group #16 group #16 group #16 group #16 group #16 group #16 group #16
 
n/a
 
2xh VMOVAPS
Vx,Wx
(SSE)
VMOVAPS
Wx,Vx
(SSE)
(no V) CVTPI2PS
Vo,Mq (SSE)
CVTPI2PS
Vo,Nq (SSE-MMX)
VMOVNTPS
Mx,Vx (SSE)
 
 
CVTTPS2PI
Pq,Wo.q
(SSE-MMX)
CVTPS2PI
Pq,Wo.q
(SSE-MMX)
VUCOMISS
Vo,Wo.d
(SSE)
VCOMISS
Vo,Wo.d
(SSE)
 
66h
 
VMOVAPD
Vx,Wx
(SSE2)
VMOVAPD
Wx,Vx
(SSE2)
(no V) CVTPI2PD
Vo,Mq (SSE2)
CVTPI2PD
Vo,Nq (SSE2-MMX)
VMOVNTPD
Mx,Vx (SSE2)
 
 
CVTTPD2PI
Pq,Wo
(SSE2-MMX)
CVTPD2PI
Pq,Wo
(SSE2-MMX)
VUCOMISD
Vo,Wo.q
(SSE2)
VCOMISD
Vo,Wo.q
(SSE2)
 
F3h
 
VCVTSI2SS
Vo,Ho,Ey
(SSE)
MOVNTSS
Md,Vo (SSE4A)
 
 
VCVTTSS2SI
Gy,Wo.d
(SSE)
VCVTSS2SI
Gy,Wo.d
(SSE)
 
F2h
 
VCVTSI2SD
Vo,Ho,Ey
(SSE2)
MOVNTSD
Mq,Vo (SSE4A)
 
 
VCVTTSD2SI
Gy,Wo.q
(SSE2)
VCVTSD2SI
Gy,Wo.q
(SSE2)
M  +
V  n
E  /
X  a
   
W=0
VMOVAPS
Vz {Kw},
Uf32 (Mzt) (K1OM)
VMOVAPS
Vz {Kw},
Sf32r (Uz) (K1OM)
VMOVAPS
Mzt {Kw},
Df32 (Vz) (K1OM)
 
 
 
M  +
V  6
E  6
X  h
   
W=1
VMOVAPD
Vz {Kw},
Uf64 (Mzt) (K1OM)
VMOVAPD
Vz {Kw},
Sf64r (Uz) (K1OM)
VMOVAPD
Mzt {Kw},
Df64 (Vz) (K1OM)
 
 
 
M  +
V  F
E  2
X  h
   
W=0
VMOVNR[NGO]APS
Mz {eh[0|1]} {Kw},
Df32 (Vz) (K1OM)
 
 
 
M  +
V  F
E  3
X  h
   
W=1
VMOVNR[NGO]APD
Mz {eh[0|1]} {Kw},
Df64 (Vz) (K1OM)
 
 
 
E  +
V  n
E  /
X  a
VMOVAPS
Vn {K} {z},
Wn (W=0)

(AVX512F,VL)
VMOVAPS
Wn {K} {z},
Vn (W=0)

(AVX512F,VL)
VMOVNTPS
Mn,Vn (W=0)
 
(AVX512F,VL)
VUCOMISS
Vo,
Wo.d {sae} (W=0)

(AVX512F)
VCOMISS
Vo,
Wo.d {sae} (W=0)

(AVX512F)
E  +
V  6
E  6
X  h
VMOVAPD
Vn {K} {z},
Wn (W=1)

(AVX512F,VL)
VMOVAPD
Wn {K} {z},
Vn (W=1)

(AVX512F,VL)
VMOVNTPD
Mn,Vn (W=1)
 
(AVX512F,VL)
VUCOMISD
Vo,
Wo.q {sae} (W=1)

(AVX512F)
VCOMISD
Vo,
Wo.q {sae} (W=1)

(AVX512F)
E  +
V  F
E  3
X  h
VCVTSI2SS
Vo,Ho,
Ed {er} (W=x)

(AVX512F)
VCVTSI2SS
Vo,Ho,
Eq {er} (W=1)

(AVX512F)
VCVTTSS2SI
Gd,
Wo.d {sae} (W=x)

(AVX512F)
VCVTTSS2SI
Gq,
Wo.d {sae} (W=1)

(AVX512F)
VCVTSS2SI
Gd,
Wo.d {er} (W=x)

(AVX512F)
VCVTSS2SI
Gq,
Wo.d {er} (W=1)

(AVX512F)
E  +
V  F
E  2
X  h
VCVTSI2SD
Vo,Ho,
Ed {er} (W=x)

(AVX512F)
VCVTSI2SD
Vo,Ho,
Eq {er} (W=1)

(AVX512F)
VCVTTSD2SI
Gd,
Wo.q {sae} (W=x)

(AVX512F)
VCVTTSD2SI
Gq,
Wo.q {sae} (W=1)

(AVX512F)
VCVTSD2SI
Gd,
Wo.q {er} (W=x)

(AVX512F)
VCVTSD2SI
Gq,
Wo.q {er} (W=1)

(AVX512F)
 
n/a
 
3xh 3 byte
opcodes

(80286+)
 
n/a
 
SMINT
(Cyrix)
SMINT
(Geode LX)
 
 
DMINT
(Geode LX)
BB0_RESET
(Cyrix GX1)
RDM
(Geode LX)
BB1_RESET
(Cyrix GX1)
 
 
CPU_WRITE
(Cyrix GX1)
 
 
CPU_READ
(Cyrix GX1)
 
 
ALTINST
(Centaur AIS)
 
n/a
 
4xh CMOVS
Gv,Ev
(see CPUID)
CMOVNS
Gv,Ev
(see CPUID)
CMOVP
Gv,Ev
(see CPUID)
CMOVNP
Gv,Ev
(see CPUID)
CMOVL
Gv,Ev
(see CPUID)
CMOVNL
Gv,Ev
(see CPUID)
CMOVLE
Gv,Ev
(see CPUID)
CMOVNLE
Gv,Ev
(see CPUID)
VEX
n/a
 
 
KMERGE2L1H
rKw,mKw (K1OM)
 
 
KMERGE2L1L
rKw,mKw (K1OM)
VEX
66h
W0
 
 
 
KADDB
rK,vK,mK (L=1)
(AVX512DQ)
 
 
 
KUNPCKBW
rK,vK,mK (L=1)
(AVX512F)
VEX
n/a
W0
 
 
 
KADDW
rK,vK,mK (L=1)
(AVX512DQ)
 
 
 
KUNPCKWD
rK,vK,mK (L=1)
(AVX512BW)
VEX
66h
W1
 
 
 
KADDD
rK,vK,mK (L=1)
(AVX512BW)
VEX
n/a
W1
 
 
 
KADDQ
rK,vK,mK (L=1)
(AVX512BW)
 
 
 
KUNPCKDQ
rK,vK,mK (L=1)
(AVX512BW)
 
n/a
 
5xh VADDPS
Vx,Hx,Wx
(SSE)
VMULPS
Vx,Hx,Wx
(SSE)
VCVTPS2PD
Vo,Wo.q
Vy,Wo
(SSE2)
VCVTDQ2PS
Vx,Wx
(SSE2)
VSUBPS
Vx,Hx,Wx
(SSE)
VMINPS
Vx,Hx,Wx
(SSE)
VDIVPS
Vx,Hx,Wx
(SSE)
VMAXPS
Vx,Hx,Wx
(SSE)
 
66h
 
VADDPD
Vx,Hx,Wx
(SSE2)
VMULPD
Vx,Hx,Wx
(SSE2)
VCVTPD2PS
Vo,Wo
Vo,Wy
(SSE2)
VCVTPS2DQ
Vx,Wx
(SSE2)
VSUBPD
Vx,Hx,Wx
(SSE2)
VMINPD
Vx,Hx,Wx
(SSE2)
VDIVPD
Vx,Hx,Wx
(SSE2)
VMAXPD
Vx,Hx,Wx
(SSE2)
 
F3h
 
VADDSS
Vo,Ho,Wo.d
(SSE)
VMULSS
Vo,Ho,Wo.d
(SSE)
VCVTSS2SD
Vo,Ho,Wo.d
(SSE2)
VCVTTPS2DQ
Vx,Wx
(SSE2)
VSUBSS
Vo,Ho,Wo.d
(SSE)
VMINSS
Vo,Ho,Wo.d
(SSE)
VDIVSS
Vo,Ho,Wo.d
(SSE)
VMAXSS
Vo,Ho,Wo.d
(SSE)
 
F2h
 
VADDSD
Vo,Ho,Wo.q
(SSE2)
VMULSD
Vo,Ho,Wo.q
(SSE2)
VCVTSD2SS
Vo,Ho,Wo.q
(SSE2)
VSUBSD
Vo,Ho,Wo.q
(SSE2)
VMINSD
Vo,Ho,Wo.q
(SSE2)
VDIVSD
Vo,Ho,Wo.q
(SSE2)
VMAXSD
Vo,Ho,Wo.q
(SSE2)
M  +
V  n
E  /
X  a
VADDPS
Vz {Kw},Hz,
Sf32 (Wzt) (W=0)

(K1OM)
VMULPS
Vz {Kw},Hz,
Sf32 (Wzt) (W=0)

(K1OM)
VCVTPS2PD
Vz {Kw},
Sf32c (Wzt.y) (W=0)

(K1OM)
VSUBPS
Vz {Kw},Hz,
Sf32 (Wzt) (W=0)

(K1OM)
M  +
V  6
E  6
X  h
VADDPD
Vz {Kw},Hz,
Sf64 (Wzt) (W=1)

(K1OM)
VMULPD
Vz {Kw},Hz,
Sf64 (Wzt) (W=1)

(K1OM)
VCVTPD2PS
Vz {Kw},
Sf64 (Wzt) (W=1)

(K1OM)
VSUBPD
Vz {Kw},Hz,
Sf64 (Wzt) (W=1)

(K1OM)
E  +
V  n
E  /
X  a
VADDPS
Vn {K} {z},Hn,
B32 (Wn) {er} (W=0)

(AVX512F,VL)
VMULPS
Vn {K} {z},Hn,
B32 (Wn) {er} (W=0)

(AVX512F,VL)
VCVTPS2PD
Vn {K} {z},
B32 (Wh) {sae} (W=0)

(AVX512F,VL)
VCVTDQ2PS
Vn {K} {z},
B32 (Wn) {er} (W=0)

(AVX512F,VL)
VCVTQQ2PS
Vh {K} {z},
B64 (Wn) {er} (W=1)

(AVX512DQ,VL)
VSUBPS
Vn {K} {z},Hn,
B32 (Wn) {er} (W=0)

(AVX512F,VL)
VMINPS
Vn {K} {z},Hn,
B32 (Wn) {sae} (W=0)

(AVX512F,VL)
VDIVPS
Vn {K} {z},Hn,
B32 (Wn) {er} (W=0)

(AVX512F,VL)
VMAXPS
Vn {K} {z},Hn,
B32 (Wn) {sae} (W=0)

(AVX512F,VL)
E  +
V  6
E  6
X  h
VADDPD
Vn {K} {z},Hn,
B64 (Wn) {er} (W=1)

(AVX512F,VL)
VMULPD
Vn {K} {z},Hn,
B64 (Wn) {er} (W=1)

(AVX512F,VL)
VCVTPD2PS
Vh {K} {z},
B64 (Wn) {er} (W=1)

(AVX512F,VL)
VCVTPS2DQ
Vn {K} {z},
B32 (Wn) {er} (W=0)

(AVX512F,VL)
VSUBPD
Vn {K} {z},Hn,
B64 (Wn) {er} (W=1)

(AVX512F,VL)
VMINPD
Vn {K} {z},Hn,
B64 (Wn) {sae} (W=1)

(AVX512F,VL)
VDIVPD
Vn {K} {z},Hn,
B64 (Wn) {er} (W=1)

(AVX512F,VL)
VMAXPD
Vn {K} {z},Hn,
B64 (Wn) {sae} (W=1)

(AVX512F,VL)
E  +
V  F
E  3
X  h
VADDSS
Vo {K} {z},Ho,
Wo.d {er} (W=0)

(AVX512F)
VMULSS
Vo {K} {z},Ho,
Wo.d {er} (W=0)

(AVX512F)
VCVTSS2SD
Vo {K} {z},Ho,
Wo.d {sae} (W=0)

(AVX512F)
VCVTTPS2DQ
Vn {K} {z},
B32 (Wn) {sae} (W=0)

(AVX512F,VL)
VSUBSS
Vo {K} {z},Ho,
Wo.d {er} (W=0)

(AVX512F)
VMINSS
Vo {K} {z},Ho,
Wo.d {sae} (W=0)

(AVX512F)
VDIVSS
Vo {K} {z},Ho,
Wo.d {er} (W=0)

(AVX512F)
VMAXSS
Vo {K} {z},Ho,
Wo.d {sae} (W=0)

(AVX512F)
E  +
V  F
E  2
X  h
VADDSD
Vo {K} {z},Ho,
Wo.q {er} (W=1)

(AVX512F)
VMULSD
Vo {K} {z},Ho,
Wo.q {er} (W=1)

(AVX512F)
VCVTSD2SS
Vo {K} {z},Ho,
Wo.q {er} (W=1)

(AVX512F)
VSUBSD
Vo {K} {z},Ho,
Wo.q {er} (W=1)

(AVX512F)
VMINSD
Vo {K} {z},Ho,
Wo.q {sae} (W=1)

(AVX512F)
VDIVSD
Vo {K} {z},Ho,
Wo.q {er} (W=1)

(AVX512F)
VMAXSD
Vo {K} {z},Ho,
Wo.q {sae} (W=1)

(AVX512F)
 
n/a
 
6xh PUNPCKHBW
Pq,Qq
(MMX)
PUNPCKHWD
Pq,Qq
(MMX)
PUNPCKHDQ
Pq,Qq
(MMX)
PACKSSDW
Pq,Qq
(MMX)
MOVDQ
Pq,Ey
(MMX)
MOVQ
Pq,Qq
(MMX)
 
66h
 
!VPUNPCKHBW
Vx,Hx,Wx
(SSE2)
!VPUNPCKHWD
Vx,Hx,Wx
(SSE2)
!VPUNPCKHDQ
Vx,Hx,Wx
(SSE2)
!VPACKSSDW
Vx,Hx,Wx
(SSE2)
!VPUNPCKL-
QDQ Vx,Hx,Wx
(SSE2) #3
!VPUNPCKH-
QDQ Vx,Hx,Wx
(SSE2)
VMOVDQ
Vo,Ey
(SSE2)
VMOVDQA
Vx,Wx
(SSE2)
 
F3h
 
VMOVDQU
Vx,Wx
(SSE2)
 
F2h
 
M  +
V  6
E  6
X  h
   
W=0
VMOVDQA32
Vz {Kw},
Ui32 (Mzt) (K1OM)
VMOVDQA32
Vz {Kw},
Si32r (Uz) (K1OM)
M  +
V  6
E  6
X  h
   
W=1
VMOVDQA64
Vz {Kw},
Ui64 (Mzt) (K1OM)
VMOVDQA64
Vz {Kw},
Si64r (Uz) (K1OM)
E  +
V  6
E  6
X  h
VPUNPCKHBW
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPUNPCKHWD
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPUNPCKHDQ
Vn {K} {z},Hn,
B32 (Wn) (W=0)

 
 
 

(AVX512F,VL)
VPACKSSDW
Vn {K} {z},Hn,
B32 (Wn) (W=0)

 
 
 

(AVX512BW,VL)
 
 
 

VPUNPCKL-
QDQ#3 Vn {K} {z},Hn,
B64 (Wn) (W=1)

(AVX512F,VL)
 
 
 

VPUNPCKH-
QDQ Vn {K} {z},Hn,
B64 (Wn) (W=1)

(AVX512F,VL)
VMOVDQ
Vo,Ey (W=x)
(AVX512F)
VMOVDQA32
Vn {K} {z},
Wn (W=0)

VMOVDQA64
Vn {K} {z},
Wn (W=1)

(AVX512F,VL)
E  +
V  F
E  3
X  h
VMOVDQU32
Vn {K} {z},
Wn (W=0)

VMOVDQU64
Vn {K} {z},
Wn (W=1)

(AVX512F,VL)
E  +
V  F
E  2
X  h
VMOVDQU8
Vn {K} {z},
Wn (W=0)

VMOVDQU16
Vn {K} {z},
Wn (W=1)

(AVX512BW,VL)
 
n/a
 
7xh VMREAD
Ey,Gy
(see CPUID)
VMWRITE
Gy,Ey
(see CPUID)
SSE5A
(AMD)
SSE5A
(AMD)
MOVDQ
Ey,Pq
(MMX)
MOVQ
Qq,Pq
(MMX)
 
66h
 
 
 
EXTRQ
Uo,Ib,Ib (/0) (SSE4A)
 
 
EXTRQ
Vo,Uo (SSE4A)
VHADDPD
Vx,Hx,Wx
(SSE3)
VHSUBPD
Vx,Hx,Wx
(SSE3)
VMOVDQ
Ey,Vo
(SSE2)
VMOVDQA
Wx,Vx
(SSE2)
 
F3h
 
VMOVQ
Vo,Wo.q
(SSE2)
VMOVDQU
Wx,Vx
(SSE2)
 
F2h
 
 
 
INSERTQ
Vo,Uo,Ib,Ib (SSE4A)
 
 
INSERTQ
Vo,Uo (SSE4A)
VHADDPS
Vx,Hx,Wx
(SSE3)
VHSUBPS
Vx,Hx,Wx
(SSE3)
M  +
V  6
E  6
X  h
   
W=0
VMOVDQA32
Mzt {Kw},
Di32 (Vz) (K1OM)
 
 
 
M  +
V  6
E  6
X  h
   
W=1
VMOVDQA64
Mzt {Kw},
Di64 (Vz) (K1OM)
 
 
 
M  +
V  F
E  3
X  h
VCVTUDQ2PD
Vz {Kw},
Si32c (Wzt.y) (W=0)

(K1OM)
E  +
V  n
E  /
X  a
VCVTTPS2UDQ
Vn {K} {z},
B32 (Wn) {sae} (W=0)

VCVTTPD2UDQ
Vh {K} {z},
B64 (Wn) {sae} (W=1)

(AVX512F,VL)
VCVTPS2UDQ
Vn {K} {z},
B32 (Wn) {er} (W=0)

VCVTPD2UDQ
Vh {K} {z},
B64 (Wn) {er} (W=1)

(AVX512F,VL)
E  +
V  6
E  6
X  h
VCVTTPS2UQQ
Vn {K} {z},
B32 (Wh) {sae} (W=0)

VCVTTPD2UQQ
Vn {K} {z},
B64 (Wn) {sae} (W=1)

(AVX512DQ,VL)
VCVTPS2UQQ
Vn {K} {z},
B32 (Wh) {er} (W=0)

VCVTPD2UQQ
Vn {K} {z},
B64 (Wn) {er} (W=1)

(AVX512DQ,VL)
VCVTTPS2QQ
Vn {K} {z},
B32 (Wh) {sae} (W=0)

VCVTTPD2QQ
Vn {K} {z},
B64 (Wn) {sae} (W=1)

(AVX512DQ,VL)
VCVTPS2QQ
Vn {K} {z},
B32 (Wh) {er} (W=0)

VCVTPD2QQ
Vn {K} {z},
B64 (Wn) {er} (W=1)

(AVX512DQ,VL)
VMOVDQ
Ey,Vo (W=x)
(AVX512F)
VMOVDQA32
Wn {K} {z},
Vn (W=0)

VMOVDQA64
Wn {K} {z},
Vn (W=1)

(AVX512F,VL)
E  +
V  F
E  3
X  h
VCVTTSS2USI
Gd,
Wo.d {sae} (W=x)

(AVX512F)
VCVTTSS2USI
Gq,
Wo.d {sae} (W=1)

(AVX512F)
VCVTSS2USI
Gd,
Wo.d {er} (W=x)

(AVX512F)
VCVTSS2USI
Gq,
Wo.d {er} (W=1)

(AVX512F)
VCVTUDQ2PD
Vn {K} {z},
B32 (Wh) {er} (W=0)

(AVX512F,VL)
VCVTUQQ2PD
Vn {K} {z},
B64 (Wn) {er} (W=1)

(AVX512DQ,VL)
VCVTUSI2SS
Vo,Ho,
Ed {er} (W=x)

(AVX512F)
VCVTUSI2SS
Vo,Ho,
Eq {er} (W=1)

(AVX512F)
VMOVQ
Vo,Wo.q (W=1)
(AVX512F)
VMOVDQU32
Wn {K} {z},
Vn (W=0)

VMOVDQU64
Wn {K} {z},
Vn (W=1)

(AVX512F,VL)
E  +
V  F
E  2
X  h
VCVTTSD2USI
Gd,
Wo.q {sae} (W=x)

(AVX512F)
VCVTTSD2USI
Gq,
Wo.q {sae} (W=1)

(AVX512F)
VCVTSD2USI
Gd,
Wo.q {er} (W=x)

(AVX512F)
VCVTSD2USI
Gq,
Wo.q {er} (W=1)

(AVX512F)
VCVTUDQ2PS
Vn {K} {z},
B32 (Wn) {er} (W=0)

(AVX512F,VL)
VCVTUQQ2PS
Vh {K} {z},
B64 (Wn) {er} (W=1)

(AVX512DQ,VL)
VCVTUSI2SD
Vo,Ho,
Ed {er} (W=x)

(AVX512F)
VCVTUSI2SD
Vo,Ho,
Eq {er} (W=1)

(AVX512F)
VMOVDQU8
Wn {K} {z},
Vn (W=0)

VMOVDQU16
Wn {K} {z},
Vn (W=1)

(AVX512BW,VL)
 
n/a
 
8xh JSDf64
Jz
(80386+)
JNSDf64
Jz
(80386+)
JPDf64
Jz
(80386+)
JNPDf64
Jz
(80386+)
JLDf64
Jz
(80386+)
JNLDf64
Jz
(80386+)
JLEDf64
Jz
(80386+)
JNLEDf64
Jz
(80386+)
 
n/a
 
9xh SETS#reg
Eb
(80386+)
SETNS#reg
Eb
(80386+)
SETP#reg
Eb
(80386+)
SETNP#reg
Eb
(80386+)
SETL#reg
Eb
(80386+)
SETNL#reg
Eb
(80386+)
SETLE#reg
Eb
(80386+)
SETNLE#reg
Eb
(80386+)
VEX
n/a
 
 
KORTEST
rKw,mKw (K1OM)
VEX
66h
W0
 
 
 
KORTESTB
rK,mK (L=0)
(AVX512DQ)
 
 
 
KTESTB
rK,mK (L=0)
(AVX512DQ)
VEX
n/a
W0
 
 
 
KORTESTW
rK,mK (L=0)
(AVX512F)
 
 
 
KTESTW
rK,mK (L=0)
(AVX512DQ)
VEX
66h
W1
 
 
 
KORTESTD
rK,mK (L=0)
(AVX512BW)
 
 
 
KTESTD
rK,mK (L=0)
(AVX512BW)
VEX
n/a
W1
 
 
 
KORTESTQ
rK,mK (L=0)
(AVX512BW)
 
 
 
KTESTQ
rK,mK (L=0)
(AVX512BW)
 
n/a
 
Axh PUSHD64
GS
(80386+)
POPD64
GS
(80386+)
RSM
(SMM)
(80386SL+?)
BTS
Ev,Gv
(80386+)
SHRD
Ev,Gv,Ib
(80386+)
SHRD
Ev,Gv,CL
(80386+)
group #15 IMUL
Gv,Ev
(80386+)
 
n/a
 
Bxh JMPE
Jz
(IA-64)
group #10
UD2

(80286+)
group #8
Ev,Ib

(80386+)
BTC
Ev,Gv
(80386+)
BSF
Gv,Ev
(80386+)
BSR
Gv,Ev
(80386+)
MOVSX
Gv,Eb
(80386+)
MOVSX
Gv,Ew
(80386+)
 
F3h
 
POPCNT
Gv,Ev
(see CPUID)
TZCNT
Gv,Ev
(see CPUID)
LZCNT
Gv,Ev
(see CPUID)
VEX
F3h
 
 
POPCNT
Gy,Ry (K1OM)
 
 
TZCNT
Gy,Ry (K1OM)
 
 
LZCNT
Gy,Ry (K1OM)
VEX
F2h
 
 
TZCNTI
Gy,Ry (K1OM)
 
n/a
 
Cxh BSWAP
rAX / r8
(80486+)
BSWAP
rCX / r9
(80486+)
BSWAP
rDX / r10
(80486+)
BSWAP
rBX / r11
(80486+)
BSWAP
rSP / r12
(80486+)
BSWAP
rBP / r13
(80486+)
BSWAP
rSI / r14
(80486+)
BSWAP
rDI / r15
(80486+)
 
n/a
 
Dxh PSUBUSB
Pq,Qq
(MMX)
PSUBUSW
Pq,Qq
(MMX)
PMINUB
Pq,Qq
(MMX-SSE)
PAND
Pq,Qq
(MMX)
PADDUSB
Pq,Qq
(MMX)
PADDUSW
Pq,Qq
(MMX)
PMAXUB
Pq,Qq
(MMX-SSE)
PANDN
Pq,Qq
(MMX)
 
66h
 
!VPSUBUSB
Vx,Hx,Wx
(SSE2)
!VPSUBUSW
Vx,Hx,Wx
(SSE2)
!VPMINUB
Vx,Hx,Wx
(SSE2)
!VPAND
Vx,Hx,Wx
(SSE2)
!VPADDUSB
Vx,Hx,Wx
(SSE2)
!VPADDUSW
Vx,Hx,Wx
(SSE2)
!VPMAXUB
Vx,Hx,Wx
(SSE2)
!VPANDN
Vx,Hx,Wx
(SSE2)
M  +
V  6
E  6
X  h
VPANDD
Vz {Kw},Hz,
Si32r (Wzt) (W=0)

VPANDQ
Vz {Kw},Hz,
Si64r (Wzt) (W=1)

(K1OM)
VPANDND
Vz {Kw},Hz,
Si32r (Wzt) (W=0)

VPANDNQ
Vz {Kw},Hz,
Si64r (Wzt) (W=1)

(K1OM)
E  +
V  6
E  6
X  h
VPSUBUSB
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPSUBUSW
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPMINUB
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPANDD
Vn {K} {z},Hn,
B32 (Wn) (W=0)

VPANDQ
Vn {K} {z},Hn,
B64 (Wn) (W=1)

(AVX512F,VL)
VPADDUSB
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPADDUSW
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPMAXUB
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPANDND
Vn {K} {z},Hn,
B32 (Wn) (W=0)

VPANDNQ
Vn {K} {z},Hn,
B64 (Wn) (W=1)

(AVX512F,VL)
 
n/a
 
Exh PSUBSB
Pq,Qq
(MMX)
PSUBSW
Pq,Qq
(MMX)
PMINSW
Pq,Qq
(MMX-SSE)
POR
Pq,Qq
(MMX)
PADDSB
Pq,Qq
(MMX)
PADDSW
Pq,Qq
(MMX)
PMAXSW
Pq,Qq
(MMX-SSE)
PXOR
Pq,Qq
(MMX)
 
66h
 
!VPSUBSB
Vx,Hx,Wx
(SSE2)
!VPSUBSW
Vx,Hx,Wx
(SSE2)
!VPMINSW
Vx,Hx,Wx
(SSE2)
!VPOR
Vx,Hx,Wx
(SSE2)
!VPADDSB
Vx,Hx,Wx
(SSE2)
!VPADDSW
Vx,Hx,Wx
(SSE2)
!VPMAXSW
Vx,Hx,Wx
(SSE2)
!VPXOR
Vx,Hx,Wx
(SSE2)
M  +
V  6
E  6
X  h
VPORD
Vz {Kw},Hz,
Si32r (Wzt) (W=0)

VPORQ
Vz {Kw},Hz,
Si64r (Wzt) (W=1)

(K1OM)
VPXORD
Vz {Kw},Hz,
Si32r (Wzt) (W=0)

VPXORQ
Vz {Kw},Hz,
Si64r (Wzt) (W=1)

(K1OM)
E  +
V  6
E  6
X  h
VPSUBSB
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPSUBSW
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPMINSW
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPORD
Vn {K} {z},Hn,
B32 (Wn) (W=0)

VPORQ
Vn {K} {z},Hn,
B64 (Wn) (W=1)

(AVX512F,VL)
VPADDSB
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPADDSW
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPMAXSW
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPXORD
Vn {K} {z},Hn,
B32 (Wn) (W=0)

VPXORQ
Vn {K} {z},Hn,
B64 (Wn) (W=1)

(AVX512F,VL)
 
n/a
 
Fxh PSUBB
Pq,Qq
(MMX)
PSUBW
Pq,Qq
(MMX)
PSUBD
Pq,Qq
(MMX)
PSUBQ
Pq,Qq
(MMX-SSE2)
PADDB
Pq,Qq
(MMX)
PADDW
Pq,Qq
(MMX)
PADDD
Pq,Qq
(MMX)
UD
(AMD)
 
66h
 
!VPSUBB
Vx,Hx,Wx
(SSE2)
!VPSUBW
Vx,Hx,Wx
(SSE2)
!VPSUBD
Vx,Hx,Wx
(SSE2)
!VPSUBQ
Vx,Hx,Wx
(SSE2)
!VPADDB
Vx,Hx,Wx
(SSE2)
!VPADDW
Vx,Hx,Wx
(SSE2)
!VPADDD
Vx,Hx,Wx
(SSE2)
M  +
V  6
E  6
X  h
VPSUBD
Vz {Kw},Hz,
Si32r (Wzt) (W=0)

(K1OM)
VPADDD
Vz {Kw},Hz,
Si32r (Wzt) (W=0)

(K1OM)
E  +
V  6
E  6
X  h
VPSUBB
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPSUBW
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPSUBD
Vn {K} {z},Hn,
B32 (Wn) (W=0)

(AVX512F,VL)
VPSUBQ
Vn {K} {z},Hn,
B64 (Wn) (W=1)

(AVX512F,VL)
VPADDB
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPADDW
Vn {K} {z},Hn,
Wn (W=x)

(AVX512BW,VL)
VPADDD
Vn {K} {z},Hn,
B32 (Wn) (W=0)

(AVX512F,VL)

notes descriptions
#1 These opcodes are not supported on pre-B0 step Pentium III processors.
#2 The condition codes are EQ, LT, LE, UNORD, NEQ, NLT, NLE, and ORD. They are encoded as the Ib, using 00...07h.
With VEX, there also are: EQ_UQ, NGE, NGT, FALSE, NEQ_OQ, GE, GT, TRUE (08...0Fh),
EQ_OS, LT_OQ, LE_OQ, UNORD_S, NEQ_US, NLT_UQ, NLE_UQ, ORD_S (10h...17h), and
EQ_US, NGE_UQ, NGT_UQ, FALSE_OS, NEQ_OS, GE_OQ, GT_OQ, TRUE_US (18...1Fh).
However, with MVEX only EQ, LT, LE, UNORD, NEQ, NLT, NLE, and ORD are valid (00...07h).
#3 Ideally the Vo,Ho,Wo variants would be Vo,Ho,Wo.q because they only use the lower half of the source operand.
#4 Ideally the Vo,Ho,Wo variants would be Vo,Ho,Wo.b because they only use the lowest byte of the source operand.



On Cyrix processors the following SMM-related opcodes can be enabled. Note that the SMINT instruction has been moved, to avoid a collision with one of the MMX instructions. Cyrix introduced the RDSHR and WRSHR instructions at the same time.

 
0Fh xxh
 
x8h x9h xAh xBh xCh xDh xEh xFh
 
7xh
 
SVDC
M10,Sw
RSDC
Sw,M10
SVLDT
M10
RSLDT
M10
SVTS
M10
RSTS
M10
SMINT



On Cyrix M2 processors the following extended MMX instructions can be enabled.

 
0Fh xxh
 
x0h x1h x2h x3h x4h x5h x6h x7h
 
5xh
 
PAVEB
Pq,Qq
PADDSIW
Pq,Qq
PMAGW
Pq,Qq
PDISTIB
Pq,Mq
PSUBSIW
Pq,Qq
 
0Fh xxh
 
x8h x9h xAh xBh xCh xDh xEh xFh
 
5xh
 
PMVZB
Pq,Mq
PMULHRW
Pq,Qq
PMVNZB
Pq,Mq
PMVLZB
Pq,Mq
PMVGEZB
Pq,Mq
PMULHRIW
Pq,Qq
PMACHRIW
Pq,Mq



On selected Centaur processors the following MM-, HE-, RNG-, and ACE-related opcodes can be enabled.

 
 
 
C0h C8h D0h D8h E0h E8h F0h F8h
 
0Fh A6h
 
MONTMUL
(MM)
XSHA1
(HE)
XSHA256
(HE)
 
0Fh A7h
 
XSTORE
(RNG)
XCRYPT-ECB
(ACE)
XCRYPT-CBC
(ACE)
XCRYPT-CTR
(ACE)
XCRYPT-CFB
(ACE)
XCRYPT-OFB
(ACE)
note While the REP prefix (F3h) is optional for the XSTORE instruction, it is mandatory for the other instructions.



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