x86 architecture
control registers




 
CR0...15
 
name 6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
MSW  
reserved
 
N
E
E
T
T
S
E
M
M
P
P
E
CR0  
reserved
 
P
G
C
D
N
W
 
reserved
 
A
M
r. W
P
 
reserved
 
N
E
E
T
T
S
E
M
M
P
P
E
CR1  
reserved
 
 
reserved
 
CR2  
page fault virtual address
 
 
page fault virtual address
 
32-bit
CR3
 
reserved
 
page directory base reserved P
C
D
P
W
T
res.
page directory pointer table base (if CR4.PAE=1)
64-bit
CR3
 
reserved
 
PML4 base #1
PML4 base #1 reserved P
CD
P
WT
res.
PCID
(implies PCD=PWT=0)
CR4  
reserved
 
 
reserved
 
C
E
T
P
K
E
S
M
A
P
S
M
E
P
 
r.
 
OS
X
SA
VE
PC
ID
E
FS
GS
BA
SE
S
E
E
S
M
X
E
V
M
X
E
VA
57
U
M
I
P
OS
XM
EX
OS
FX
SR
P
C
E
P
G
E
M
C
E
P
A
E
P
S
E
D
E
T
S
D
P
V
I
V
M
E
CR5  
reserved
 
 
reserved
 
CR6  
reserved
 
 
reserved
 
CR7  
reserved
 
 
reserved
 
CR8  
reserved
 
 
reserved
 
 
TPR
 
CR9  
reserved
 
 
reserved
 
CR10  
reserved
 
 
reserved
 
CR11  
reserved
 
 
reserved
 
CR12  
reserved
 
 
reserved
 
CR13  
reserved
 
 
reserved
 
CR14  
reserved
 
 
reserved
 
CR15  
reserved
 
 
reserved
 
note description
#1 The number of actually implemented bits depends on the number of physical address bits.
The remaining bits are reserved if less than 52 physical address bits are implemented.



 
XCR0
 
name 6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
 
XCR0
 
r
e
s
L
W
P
reserved
reserved C
E
T
S
C
E
T
U
r
e
s
P
K
R
U
T
P
C
S
V
16
...
31
V
5
1
2
K
r
e
g
BN
DC
SR
B
r
e
g
Y
M
M
X
M
M
X
8
7



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