Unfortunately the definition of the TSC is somewhat lax.

It merely specifies that the TSC value is incremented once during every
processor clock cycle, even during HLT or STPCLK, and that the value is
monotonically increasing for successive RDTSCs (errata aside). However,
it does not specify the actual clock that is used to increment the TSC.
It could be the current core clock. But it could as well be a faster or
slower clock, used for a portion of the processor. Or the nominal clock
at which the processor is rated, regardless of its current clock. Heck,
it could even be a completely arbitrary clock.

For example, the TSC value of my 866 MHz Crusoe appears to increment at
a rate of 866 million times per second, regardless of the current clock
frequency (which LongRun can vary from 300 to 866 MHz).

Another easily forgotten aspect is that while instruction timing can be
predicted, the complexity of doing so can be quite enormous.

After all, there aren't just pipelines, caches, buffers, memory, and so
on, but also implementations that are based on dynamic translation.

Just my $0.02.