Intel P55
| General Details | Name | Pentium with MMX technology | |
| Codename | A80503, P55 | ||
| Family/Generation | 80586, 5th Generation, MMX | ||
| Vendor | Intel | ||
| Manufacturer | Intel | ||
| First Introduction |
Jan 8, 1997 (166 and 200 MHz, 150 MHz TCP) Mar 3, 1997 (125, 150, and 166 MHz Overdrive) May 19, 1997 (133 MHz TCP) Jun 2, 1997 (233 MHz) Aug 4, 1997 (180 and 200 MHz Overdrive) Sep 8, 1997 (200 and 233 MHz TCP) Jan 12, 1998 (266 MHz TCP) Oct 13, 1998 (166 and 266 MHz embedded) Jan 7, 1999 (300 MHz TCP) |
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| Physical Details | Package Type |
296 Pin PGA 296 Pin PPGA 320 Pin PGA (Overdrive) 320 Lead TCP 352 Pin PBGA |
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| Package Size |
4.95 cm x 4.95 cm (PGA) 4.95 cm x 4.95 cm (PPGA) 2.40 cm x 2.40 cm (TCP) 3.50 cm x 3.50 cm (PBGA) |
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| Socket or Slot | Socket 7 | ||
| Transistors | 4,500,000 (includes 2x 16 KB L1 Cache) | ||
| Process Technology |
4M, 0.28 µm, CMOS (up to 233 MHz) 4M, 0.25 µm, CMOS (up to 266 MHz) |
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| Die Size |
140, then 128 mm² (0.28 µm) 90 mm² (0.25 µm) |
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| Electrical Details | Split Voltage | Yes (determined via Motherboard) | |
| Core Voltage |
3.3 V (OverDrive) 2.8 V 2.45 V (0.28 µm TCP) 2.0 V (0.25 µm TCP @ 266 and 300 MHz) 1.9 V (0.25 µm PPGA embedded) 1.8 V (0.25 µm PBGA embedded) 1.8 V (0.25 µm TCP) |
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| I/O Voltage |
3.3 V (0.28 µm) 2.5 V (0.25 µm) |
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| Typical Power |
166 MHz: 6.1 W (0.28 µm) 200 MHz: 7.3 W (0.28 µm) 233 MHz: 7.9 W (0.28 µm) 133 MHz: 4.4 W (0.28 µm TCP) 150 MHz: 5.0 W (0.28 µm TCP) 166 MHz: 5.5 W (0.28 µm TCP) 166 MHz: 2.3 W (0.25 µm TCP) 200 MHz: 2.7 W (0.25 µm TCP) 233 MHz: 3.0 W (0.25 µm TCP) 266 MHz: 4.5 W (0.25 µm TCP) 300 MHz: 5.0 W (0.25 µm TCP) 166 MHz: 2.9 W (0.25 µm embedded) 266 MHz: 4.5 W (0.25 µm embedded) |
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| Maximum Power |
166 MHz: 13.1 W (0.28 µm) 200 MHz: 15.7 W (0.28 µm) 233 MHz: 17.0 W (0.28 µm) 125, 150, 166 and 180 MHz Overdrive: 15.0 W 200 MHz Overdrive: 16.5 W 133 MHz: 7.8 W (0.28 µm TCP) 150 MHz: 8.6 W (0.28 µm TCP) 166 MHz: 9.0 W (0.28 µm TCP) 166 MHz: 4.1 W (0.25 µm TCP) 200 MHz: 5.0 W (0.25 µm TCP) 233 MHz: 5.5 W (0.25 µm TCP) 266 MHz: 7.6 W (0.25 µm TCP) 300 MHz: 8.4 W (0.25 µm TCP) 166 MHz: 4.1 W (0.25 µm embedded PBGA) 166 MHz: 4.5 W (0.25 µm embedded PPGA) 266 MHz: 7.6 W (0.25 µm embedded) |
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| Cooling | Required | ||
| Clock Frequencies | CPU Core Speed |
133, 150, 166, 180, 200, 233, 266, 300 MHz 125, 150, 166, 180, 200 MHz (Overdrive) |
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| L1 Cache Speed | 1.0x Core Speed | ||
| L2 Cache Speed | 1.0x External Bus Speed | ||
| External Bus Speed | 60 or 66 MHz | ||
| Core/Bus Ratio | 2.0x, 2.5x, 3.0x, 3.5x, 4.0x, 4.5x | ||
| Miscellaneous | usual Motherboard | Single or Dual Processor Socket 7 | |
| usual Chipset | Intel 82430FX, 82430HX, 82430VX, 82430TX, or non-Intel | ||
| Pictures |
0.28 µm Die and PPGA Package (52 KB JPG) 0.28 µm Die and TCP Package (35 KB JPG) CPUID=0543h CPGA Top (44 KB JPG) and Bottom (106 KB JPG) CPUID=0543h PPGA Top (124 KB JPG) and Bottom (100 KB JPG) Mobile Module MMC-1 Top (120 KB JPG) and Bottom (131 KB JPG) Module with Unpackaged Die (60 KB JPG) and Bottom (45 KB JPG) |
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| Processor Core | Generic Details | CISC, In-order and Pipelined Execution | |
| Specific Details | Dual Pipeline Design | ||
| Registers | 32 Bit Integer, 80 Bit FP, 64 Bit MM | ||
| Pipeline Depth | 3 (Shared) plus 2x 3 (Dual Pipeline) Stages | ||
| Instruction Decoder | 2x IA-32/Cycle | ||
| Execution Units | 2x Integer/MMX, Pipelined FPU | ||
| Execution Speed | up to 2x IA-32/Cycle | ||
| Processor Buses | Address Bus Width | 32 Bit | |
| Data Bus Width | 64 Bit | ||
| Physical Memory | 2^32 Bit = 4 GB | ||
| Virtual Memory | 2^32 Bit = 4 GB | ||
| Logical Memory | (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB) | ||
| Multiprocessing | SMP, 2 Processors, using integrated local APICs | ||
| Power Management | HLT, STPCLK, SMI/SMM | ||
| Processor Caches | Level 0 | N/A | |
| Level 1 | Code |
16 KB, 4-Way, 32 Byte/Line, SI, Fetch Port (no Split-line Access Support), Snoop Port (for SMC), LRU |
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| Data |
16 KB, 4-Way, 32 Byte/Line, MESI, Non-Blocking, Dual-ported, Snoop Port, 8 Banks, LRU |
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| Level 2 | Unified | External, depends on Motherboard | |
| Processor Buffers | Read Buffer |
32 Byte for Code Cache 32 Byte for Data Cache |
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| Write Buffer |
4x 8 Byte (supports Dual Pipeline Design) 3x 32 Byte (Line Replacement Write Buffer, Internal and External Snoop Write Buffer) |
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| Prefetch Queue |
4x 16 Byte (supports Dual Pipeline Design) SMC can be observed up to 94 Byte ahead |
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| Branch Prediction | Static | Yes | |
| Dynamic |
256 Entries, 16-Way, providing 16x 4-State Pattern Recognition |
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| RSB | 4 Entries | ||
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TLB see US patent 5,928,352 for details on the 4K/4M implementation see US patent 5,860,147 for details on the replacement strategy |
4 KB Code | 32 Entries, Full, LRU | |
| 4 MB Code | |||
| 4 KB Data | 64 Entries, Full, LRU | ||
| 4 MB Data | |||
| Instruction Set | Regular | IA-32 | |
| Floating Point | Integrated | ||
| Multi Media | MMX | ||
| Processor Modes | Real, Protected, Virtual, Paging, SMM, Probe Mode | ||
