Intel P54
| General Details | Name | Pentium | |
| Codename | A80502, P54 | ||
| Family/Generation | 80586, 5th Generation | ||
| Vendor | Intel | ||
| Manufacturer | Intel | ||
| First Introduction |
Mar 7, 1994 (90 and 100 MHz) Oct 10, 1994 (75 MHz) Mar 27, 1995 (120 MHz) Jun 12, 1995 (133 MHz) Jan 4, 1996 (150 and 166 MHz) Mar 4, 1996 (125, 150, and 166 MHz Overdrive) Jun 10, 1996 (200 MHz) |
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| Physical Details | Package Type |
296 Pin PGA 296 Pin PPGA 320 Pin PGA (Overdrive) 320 Lead TCP |
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| Package Size |
4.95 cm x 4.95 cm (PGA) 4.95 cm x 4.95 cm (PPGA) 2.40 cm x 2.40 cm (TCP) |
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| Socket or Slot |
Socket 5 (up to 133 MHz) Socket 5 (up to 166 MHz Overdrive) Socket 7 (up to 200 MHz) |
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| Transistors |
3,200,000 (0.50 µm, includes 2x 8 KB L1 Cache) 3,300,000 (0.35 µm, includes 2x 8 KB L1 Cache) |
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| Process Technology |
4M, 0.50 µm, BiCMOS (up to 120 MHz) 4M, 0.35 µm, BiCMOS (up to 200 MHz) |
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| Die Size |
148 mm² (0.50 µm) 91, then 83 mm² (0.35 µm) |
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| Electrical Details | Split Voltage | N/A | |
| Core Voltage |
3.3 V (STD) 3.52 V (VRE) |
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| I/O Voltage |
3.3 V (STD) 3.52 V (VRE) |
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| Typical Power |
75 MHz: 3.0 W 90 MHz: 3.5 W 100 MHz: 3.9 W 120 MHz: 5.1 W 133 MHz: 4.3 W 150 MHz: 4.9 W 166 MHz: 5.4 W 200 MHz: 6.5 W |
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| Maximum Power |
75 MHz: 8.0 W 90 MHz: 9.0 W 100 MHz: 10.1 W 120 MHz: 12.8 W 133 MHz: 11.2 W 150 MHz: 11.6 W 166 MHz: 14.5 W 200 MHz: 15.5 W 125, 150, and 166 MHz Overdrive: 15.0 W |
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| Cooling | Required | ||
| Clock Frequencies | CPU Core Speed |
75, 90, 100, 120, 133, 150, 166, 200 MHz 125, 150, 166 MHz (Overdrive) |
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| L1 Cache Speed | 1.0x Core Speed | ||
| L2 Cache Speed | 1.0x External Bus Speed | ||
| External Bus Speed | 50, 60, or 66 MHz | ||
| Core/Bus Ratio | 1.5x, 2.0x, 2.5x, 3.0x | ||
| Miscellaneous | usual Motherboard | Single or Dual Processor Socket 5 or 7 | |
| usual Chipset | Intel 82430LX, 82430NX, 82430FX, 82430HX, 82430VX, 82430TX, or non-Intel | ||
| Pictures |
0.35 µm Die (142 KB JPG) CPUID=0521h Top (63 KB JPG) and Bottom (105 KB JPG) CPUID=0525h Top (52 KB JPG) and Bottom (104 KB JPG) CPUID=0526h Top (56 KB JPG) and Bottom (117 KB JPG) CPUID=052Bh Top (71 KB JPG) and Bottom (103 KB JPG) CPUID=052Ch Top (71 KB JPG) and Bottom (108 KB JPG) TCP Package (10 KB JPG) |
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| Processor Core | Generic Details | CISC, In-order and Pipelined Execution | |
| Specific Details | Dual Pipeline Design | ||
| Registers | 32 Bit Integer, 80 Bit FP | ||
| Pipeline Depth | 2 (Shared) plus 2x 3 (Dual Pipeline) Stages | ||
| Instruction Decoder | 2x IA-32/Cycle | ||
| Execution Units | 2x Integer, Pipelined FPU | ||
| Execution Speed | up to 2x IA-32/Cycle | ||
| Processor Buses | Address Bus Width | 32 Bit | |
| Data Bus Width | 64 Bit | ||
| Physical Memory | 2^32 Bit = 4 GB | ||
| Virtual Memory | 2^32 Bit = 4 GB | ||
| Logical Memory | (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB) | ||
| Multiprocessing | SMP, 2 Processors, using integrated local APICs | ||
| Power Management | HLT, STPCLK, SMI/SMM | ||
| Processor Caches | Level 0 | N/A | |
| Level 1 | Code |
8 KB, 2-Way, 32 Byte/Line, SI, 2x Fetch Port (supports Split-line Acess), Snoop Port (for SMC), LRU |
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| Data |
8 KB, 2-Way, 32 Byte/Line, MESI, Non-blocking, Dual-ported, Snoop Port, 8 Banks, LRU |
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| Level 2 | Unified | External, depends on Motherboard | |
| Processor Buffers | Read Buffer |
32 Byte for Code Cache 32 Byte for Data Cache |
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| Write Buffer |
2x 8 Byte (supports Dual Pipeline Design) 3x 32 Byte (Line Replacement Write Buffer, Internal and External Snoop Write Buffer) |
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| Prefetch Queue |
2x 32 Byte (supports Dual Pipeline Design) SMC can be observed up to 94 Byte ahead |
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| Branch Prediction | Static | Yes | |
| Dynamic | 256 Entries, 4-Way, 4-State, Random | ||
| RSB | N/A | ||
| TLB | 4 KB Code | 32 Entries, 4-Way, LRU | |
| 4 MB Code | N/A (uses 4 KB Code Entries) | ||
| 4 KB Data | 64 Entries, 4-Way, LRU | ||
| 4 MB Data | 8 Entries, 4-Way, LRU | ||
| Instruction Set | Regular | IA-32 | |
| Floating Point | Integrated | ||
| Multi Media | N/A | ||
| Processor Modes | Real, Protected, Virtual, Paging, SMM, Probe Mode | ||
