Intel P5
| General Details | Name | Pentium | |
| Codename | A80501, P5 | ||
| Family/Generation | 80586, 5th Generation | ||
| Vendor | Intel | ||
| Manufacturer | Intel | ||
| First Introduction | Mar 22, 1993 (60 and 66 MHz) | ||
| Physical Details | Package Type | 273 Pin PGA | |
| Package Size | 5.49 cm x 5.49 cm | ||
| Socket or Slot | Socket 4 | ||
| Transistors | 3,100,000 (includes 2x 8 KB L1 Cache) | ||
| Process Technology | 3M, 0.80 µm, BiCMOS | ||
| Die Size | 294 mm² (0.80 µm) | ||
| Electrical Details | Split Voltage | N/A | |
| Core Voltage | 5.0 V | ||
| I/O Voltage | 5.0 V | ||
| Typical Power |
60 MHz: 11.9 W 66 MHz: 13.0 W |
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| Maximum Power |
60 MHz: 14.6 W 66 MHz: 16.0 W |
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| Cooling | Required | ||
| Clock Frequencies | CPU Core Speed | 60, 66 MHz | |
| L1 Cache Speed | 1.0x Core Speed | ||
| L2 Cache Speed | 1.0x External Bus Speed | ||
| External Bus Speed | 60, 66 MHz | ||
| Core/Bus Ratio | 1.0x | ||
| Miscellaneous | usual Motherboard | Single or Dual Processor Socket 4 | |
| usual Chipset | Intel 82430LX, 82430NX | ||
| Pictures |
CPUID=0512h Top (53 KB JPG) and Bottom (141 KB JPG) CPUID=0513h Top (67 KB JPG) and Bottom (155 KB JPG) CPUID=0515h Top (68 KB JPG) and Bottom (152 KB JPG), 60 MHz CPUID=0515h Top (68 KB JPG) and Bottom (148 KB JPG), 66 MHz CPUID=0517h Top (78 KB JPG) and Bottom (158 KB JPG) |
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| Processor Core | Generic Details | CISC, In-order and Pipelined Execution | |
| Specific Details | Dual Pipeline Design | ||
| Registers | 32 Bit Integer, 80 Bit FP | ||
| Pipeline Depth | 2 (Shared) plus 2x 3 (Dual Pipeline) Stages | ||
| Instruction Decoder | 2x IA-32/Cycle | ||
| Execution Units | 2x Integer, Pipelined FPU | ||
| Execution Speed | up to 2x IA-32/Cycle | ||
| Processor Buses | Address Bus Width |
36 Bit (Samples) 32 Bit (Production) |
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| Data Bus Width | 64 Bit | ||
| Physical Memory |
2^36 Bit = 64 GB (Samples) 2^32 Bit = 4 GB (Production) |
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| Virtual Memory | 2^32 Bit = 4 GB | ||
| Logical Memory | (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB) | ||
| Multiprocessing | SMP, 2 Processors, using external APIC | ||
| Power Management | HLT, SMI/SMM | ||
| Processor Caches | Level 0 | N/A | |
| Level 1 | Code |
8 KB, 2-Way, 32 Byte/Line, SI, 2x Fetch Port (supports Split-line Acess), Snoop Port (for SMC), LRU |
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| Data |
8 KB, 2-Way, 32 Byte/Line, MESI, Non-blocking, Dual-ported, Snoop Port, 8 Banks, LRU |
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| Level 2 | Unified | External, depends on Motherboard | |
| Processor Buffers | Read Buffer |
32 Byte for Code Cache 32 Byte for Data Cache |
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| Write Buffer |
2x 8 Byte (supports Dual Pipeline Design) 3x 32 Byte (Line Replacement Write Buffer, Internal and External Snoop Write Buffer) |
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| Prefetch Queue |
2x 32 Byte (supports Dual Pipeline Design) SMC can be observed up to 94 Byte ahead |
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| Branch Prediction | Static | Yes | |
| Dynamic | 256 Entries, 4-Way, 4-State, Random | ||
| RSB | N/A | ||
| TLB | 4 KB Code | 32 Entries, 4-Way, LRU | |
| 4 MB Code | N/A (uses 4 KB Code Entries) | ||
| 4 KB Data | 64 Entries, 4-Way, LRU | ||
| 4 MB Data | 8 Entries, 4-Way, LRU | ||
| Instruction Set | Regular | IA-32 | |
| Floating Point | Integrated | ||
| Multi Media | N/A | ||
| Processor Modes | Real, Protected, Virtual, Paging, SMM, Probe Mode | ||
