Intel P4 (incl. Celeron and Xeon)
| General Details | Name |
Celeron (Low End) Pentium 4 (Mid Range) Pentium 4 Extreme Edition (Gaming) Pentium Xeon and Xeon MP (High End) mobile Celeron and Pentium 4M (Mobile) |
|
| Codename |
Jackson Technology (HTT) Yamhill Technology (EM64T) Willamette (0.18 µm), Foster (Xeon), Foster MP (On-Die L3) Northwood (0.13 µm), Prestonia (Xeon), Gallatin (On-Die L3) Prescott (0.09 µm 1 MB L2), Smithfield (0.09 µm 1 MB L2 DC) Nocona (0.09 µm 1 MB L2 Xeon DP), Cranford (0.09 µm 1 MB L2 Xeon MP) Potomac (0.09 µm 1 MB L2 Xeon MP On-Die L3) Irwindale (0.09 µm 2 MB L2), Paxville (0.09 µm 2 MB L2 DC) Cedar Mill (65 nm 2 MB L2), Presler (65 nm 2 MB L2 MCM) Dempsey (65 nm 2 MB L2 MCM Xeon DP) Tulsa (65 nm 1 MB L2 DC Xeon MP On-Die L3) |
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| Family/Generation | 80786, 7th Generation, MMX, SSE, SSE2, SSE3 (0.09 µm) | ||
| Vendor | Intel | ||
| Manufacturer | Intel | ||
| First Introduction |
Feb 20, 2000 (1.5 GHz demo @ IDF, 0.18 µm) Nov 20, 2000 (1.4 and 1.5 GHz PGA423) Jan 3, 2001 (1.3 GHz PGA423) Apr 23, 2001 (1.7 GHz PGA423) May 21, 2001 (1.4, 1.5, and 1.7 GHz PGA603) Jul 2, 2001 (1.6 and 1.8 GHz PGA423) Aug 13, 2001 (2.0 GHz demo @ Siggraph, 0.18 µm) Aug 27, 2001 (1.9 and 2.0 GHz PGA423 and µPGA478) Aug 28, 2001 (3.5 GHz demo @ IDF, 0.13 µm, super-cooled) Sep 25, 2001 (2.0 GHz PGA603) Jan 7, 2002 (2.0 and 2.2 GHz µPGA478 0.13 µm) Jan 7, 2002 (1.6, 1.8, and 2.0 GHz µPGA478 0.13 µm, sub-45W) Jan 7, 2002 (1.8, 2.0 and 2.2 GHz PGA603 0.13 µm) Feb 25, 2002 (1.8, 2.0, and 2.2 GHz PGA603 0.13 µm HTT) Feb 26, 2002 (4.0 GHz demo @ IDF, 0.13 µm, super-cooled) Mar 3, 2002 (1.6/1.2 and 1.7/1.2 GHz µFCPGA478 0.13 µm*) Mar 12, 2002 (1.4 and 1.5 GHz PGA603 0.18 µm HTT 512 KB L3) Mar 12, 2002 (1.6 GHz PGA603 0.18 µm HTT 1024 KB L3) Apr 2, 2002 (2.4 GHz µPGA478 0.13 µm, 300 mm Wafers) Apr 23, 2002 (2.4 GHz µPGA603 0.13 µm, 300 mm Wafers) Apr 23, 2002 (1.4/1.2 GHz µFCPGA478 0.13 µm*) Apr 23, 2002 (1.5/1.2 GHz µFCPGA478 0.13 µm*) Apr 23, 2002 (1.8/1.2 GHz µFCPGA478 0.13 µm*) May 6, 2002 (2.26B, 2.40B, and 2.53B GHz µPGA478 0.13 µm) May 15, 2002 (1.7 GHz µPGA478 0.18 µm Celeron) Jun 12, 2002 (1.8 GHz µPGA478 0.18 µm Celeron) Jun 24, 2002 (1.9/1.2 GHz µFCPGA478 0.13 µm*) Jun 24, 2002 (2.0/1.2 GHz µFCPGA478 0.13 µm*) Jun 24, 2002 (1.4 GHz µFCPGA478 0.13 µm mobile Celeron) Jun 24, 2002 (1.5 GHz µFCPGA478 0.13 µm mobile Celeron) Aug 26, 2002 (2.5, 2.6, 2.66B, and 2.8B GHz µPGA478 0.13 µm) Sep 11, 2002 (2.6 and 2.8 GHz PGA603 0.13 µm) Sep 16, 2002 (1.6 GHz µFCPGA478 0.13 µm mobile Celeron) Sep 16, 2002 (1.7 GHz µFCPGA478 0.13 µm mobile Celeron) Sep 16, 2002 (1.8 GHz µFCPGA478 0.13 µm mobile Celeron) Sep 16, 2002 (2.2/1.2 GHz µFCPGA478 0.13 µm*) Sep 18, 2002 (2.0 GHz µPGA478 0.13 µm Celeron) Nov 4, 2002 (1.5 and 1.9 GHz PGA603 0.13 µm 1024 KB L3) Nov 4, 2002 (2.0 GHz PGA603 0.13 µm 2048 KB L3) Nov 14, 2002 (3.06B GHz µPGA478 0.13 µm HTT) Nov 18, 2002 (2.0B, 2.4B, 2.66B, 2.8B GHz PGA603 0.13 µm) Nov 20, 2002 (2.1 and 2.2 GHz µPGA478 0.13 µm Celeron) Jan 14, 2003 (2.0 GHz µFCPGA478 0.13 µm mobile Celeron) Jan 14, 2003 (2.4/1.2 GHz µFCPGA478 0.13 µm*) Mar 10, 2003 (3.0 and 3.06B GHz PGA603 0.13 µm) Mar 31, 2003 (2.3 and 2.4 GHz µPGA478 0.13 µm Celeron) Apr 14, 2003 (3.0D GHz µPGA478 0.13 µm HTT) Apr 16, 2003 (2.2 GHz µFCPGA478 0.13 µm mobile Celeron) Apr 16, 2003 (2.5/1.2 GHz µFCPGA478 0.13 µm*) May 21, 2003 (2.4D/2.6D/2.8D GHz µPGA478 0.13 µm HTT) Jun 11, 2003 (2.2, 2.3, and 2.4 GHz µPGA478 0.13 µm Celeron) Jun 11, 2003 (2.4 GHz µFCPGA478 0.13 µm mobile Celeron) Jun 11, 2003 (2.40B/1.20B GHz µFCPGA478 0.13 µm*) Jun 11, 2003 (2.66B/1.20B GHz µFCPGA478 0.13 µm*) Jun 11, 2003 (2.80B/1.20B GHz µFCPGA478 0.13 µm*) Jun 11, 2003 (3.06B/1.20B GHz µFCPGA478 0.13 µm*) Jun 11, 2003 (2.6/1.2 GHz µFCPGA478 0.13 µm*) Jun 23, 2003 (3.2D GHz µPGA478 0.13 µm HTT) Jun 25, 2003 (2.5 and 2.6 GHz µPGA478 0.13 µm Celeron) Jun 30, 2003 (2.0 GHz PGA603 0.13 µm 1024 KB L3) Jun 30, 2003 (2.5 GHz PGA603 0.13 µm 1024 KB L3) Jun 30, 2003 (2.8 GHz PGA603 0.13 µm 2048 KB L3) Jul 14, 2003 (3.06B GHz PGA603 0.13 µm 1024 KB L3) Sep 23, 2003 (2.66B/1.60B GHz µFCPGA478 0.13 µm HTT*) Sep 23, 2003 (2.80B/1.60B GHz µFCPGA478 0.13 µm HTT*) Sep 23, 2003 (3.06B/1.60B GHz µFCPGA478 0.13 µm HTT*) Sep 23, 2003 (3.20B/1.60B GHz µFCPGA478 0.13 µm HTT*) Sep 24, 2003 (2.7 GHz µPGA478 0.13 µm Celeron) Oct 6, 2003 (3.20B GHz PGA603 0.13 µm 1024 KB L3) Nov 3, 2003 (3.2D-EE GHz µPGA478 0.13 µm HTT 2048 KB L3) Nov 5, 2003 (2.8 GHz µPGA478 0.13 µm Celeron) Nov 12, 2003 (2.5 GHz µFCPGA478 0.13 µm mobile Celeron) Feb 2, 2004 (3.4D GHz µPGA478 0.13 µm HTT) Feb 2, 2004 (3.4D-EE GHz µPGA478 0.13 µm HTT 2048 KB L3) Feb 2, 2004 (2.80B GHz µPGA478 0.09 µm) Feb 2, 2004 (2.8D GHz µPGA478 0.09 µm HTT) Feb 2, 2004 (3.0D GHz µPGA478 0.09 µm HTT) Feb 2, 2004 (3.2D GHz µPGA478 0.09 µm HTT) Feb 2, 2004 (3.4D GHz µPGA478 0.09 µm HTT) Mar 2, 2004 (2.2 GHz PGA603 0.13 µm 2048 KB L3) Mar 2, 2004 (2.7 GHz PGA603 0.13 µm 2048 KB L3) Mar 2, 2004 (3.0 GHz PGA603 0.13 µm 4096 KB L3) May ???, 2004 (1.2 GHz µFCPGA478 0.13 µm embedded Celeron) Jun 1, 2004 (518: 2.80B GHz µFCPGA478 0.09 µm HTT DTR) Jun 1, 2004 (532: 3.06B GHz µFCPGA478 0.09 µm HTT DTR) Jun 1, 2004 (538: 3.20B GHz µFCPGA478 0.09 µm HTT DTR) Jun 21, 2004 (3.4D-EE GHz LGA775 0.13 µm HTT 2048 KB L3) Jun 21, 2004 (2.80B GHz LGA775 0.09 µm) Jun 21, 2004 (520: 2.8D GHz LGA775 0.09 µm HTT) Jun 21, 2004 (530: 3.0D GHz LGA775 0.09 µm HTT) Jun 21, 2004 (540: 3.2D GHz LGA775 0.09 µm HTT) Jun 21, 2004 (550: 3.4D GHz LGA775 0.09 µm HTT) Jun 21, 2004 (560: 3.6D GHz LGA775 0.09 µm HTT) Jun 24, 2004 (320: 2.40B GHz µFCPGA478 0.09 µm Celeron) Jun 24, 2004 (325: 2.53B GHz µFCPGA478 0.09 µm Celeron) Jun 24, 2004 (330: 2.66B GHz µFCPGA478 0.09 µm Celeron) Jun 24, 2004 (335: 2.80B GHz µFCPGA478 0.09 µm Celeron) Jun 28, 2004 (2.8D GHz PGA603 0.09 µm EM64T) Jun 28, 2004 (3.0D GHz PGA603 0.09 µm EM64T) Jun 28, 2004 (3.2D GHz PGA603 0.09 µm EM64T) Jun 28, 2004 (3.4D GHz PGA603 0.09 µm EM64T) Jun 28, 2004 (3.6D GHz PGA603 0.09 µm EM64T) * with SpeedStep Technology |
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| Physical Details | Package Type |
423 Pin PGA 478 Pin µPGA 603 Pin PGA 478 Pin µFCPGA (no Integrated Heat Spreader) 775 Contact LGA |
|
| Package Size |
5.34 cm x 5.34 cm (PGA423) 3.50 cm x 3.50 cm (µPGA478) 5.34 cm x 5.34 cm (PGA603) 3.75 cm x 3.75 cm (LGA775) |
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| Socket or Slot |
PGA423 µPGA478 PGA603 LGA775 |
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| Transistors |
42,000,000 (includes 12 K µOP TC + 8 KB L1d + 128 KB L2 Cache) 42,000,000 (includes 12 K µOP TC + 8 KB L1d + 256 KB L2 Cache) ??,???,??? (same as above + 512 KB L3 Cache) 110,000,000 (same as above + 1024 KB L3 Cache) 55,000,000 (includes 12 K µOP TC + 8 KB L1d + 256 KB L2 Cache) 55,000,000 (includes 12 K µOP TC + 8 KB L1d + 512 KB L2 Cache) ??,???,??? (same as above + 1024 KB L3 Cache) 178,000,000 (same as above + 2048 KB L3 Cache) ???,???,??? (same as above + 4096 KB L3 Cache) 125,000,000 (includes 12 K µOP TC + 16 KB L1d + 1024 KB L2) 164,000,000 (includes 12 K µOP TC + 16 KB L1d + 2048 KB L2) ???,???,??? (same as below + 4096 KB L3 Cache) 675,000,000 (same as below + 8192 KB L3 Cache) 230,000,000 (includes 12 K µOP TC + 16 KB L1d + 1024 KB L2 DC) 322,000,000 (includes 12 K µOP TC + 16 KB L1d + 2048 KB L2 DC) 188,000,000 (includes 12 K µOP TC + 16 KB L1d + 2048 KB L2) 376,000,000 (includes 12 K µOP TC + 16 KB L1d + 2048 KB L2 DC) 1.328 B. (12 K µOP TC + 16 KB L1d + 1024 KB L2 DC + 16 MB L3) |
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| Process Technology |
6M, 0.18 µm, CMOS 6M, 0.13 µm, CMOS, Cu, Low-K 7M, 0.09 µm, CMOS, Cu, Low-K Inter-Layer, Strained Si 8M, 65 nm, CMOS, Cu, Low-K Inter-Layer, 2nd Gen Strained Si |
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| Die Size |
217 mm² (0.18 µm with 128 KB L2 Cache) 217 mm² (0.18 µm with 256 KB L2 Cache) ??? mm² (same as above + 512 KB L3 Cache) ??? mm² (same as above + 1024 KB L3 Cache) 131 mm² (0.13 µm with 256 KB L2 Cache) 146 mm² (0.13 µm with 512 KB L2 Cache), then 131 mm² ??? mm² (same as above + 1024 KB L3 Cache) 237 mm² (same as above + 2048 KB L3 Cache) ??? mm² (same as above + 4096 KB L3 Cache) 112 mm² (0.09 µm with 1024 KB L2 Cache) 135 mm² (0.09 µm with 2048 KB L2 Cache) ??? mm² (same as below + 4096 KB L3 Cache) 354 mm² (same as below + 8192 KB L3 Cache) 206 mm² (0.09 µm with 1024 KB L2 Cache DC) 299 mm² (0.09 µm with 2048 KB L2 Cache DC) ??? mm² (65 nm with 2048 KB L2 Cache) 162 mm² (65 nm with 2048 KB L2 Cache DC) 435 mm² (65 nm with 1024 KB L2 Cache DC + 16 MB L3 Cache) |
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| Electrical Details | Split Voltage | No (automatically determined via VID Pins) | |
| Core Voltage |
1.750 V (0.18 µm) 1.700 V (0.18 µm) 1.550 V (0.13 µm) 1.525 V (0.13 µm) 1.500 V (0.13 µm) 1.500 V (0.13 µm MP with 4096 KB L3 Cache) 1.475 V (0.13 µm MP) 1.425 V (0.09 µm) 1.400 V (0.09 µm) 1.325 V (0.09 µm DTR) 1.300 V (0.13 µm mobile) 1.550/1.200 V (0.13 µm mobile B above 3 GHz*) 1.525/1.200 V (0.13 µm mobile B up to 3 GHz*) 1.300/1.200 V (0.13 µm mobile A*) * with SpeedStep Technology |
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| L2 Voltage | same as Core Voltage | ||
| L3 Voltage | same as Core Voltage | ||
| I/O Voltage |
same as Core Voltage 3.3 V for SMBus (Xeon) |
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| Typical Power |
48.9 W (1.3 GHz 0.18 µm PGA423 @ 1.70 V) 51.8 W (1.4 GHz 0.18 µm PGA423 @ 1.70 V) 54.7 W (1.5 GHz 0.18 µm PGA423 @ 1.70 V) 51.6 W (1.3 GHz 0.18 µm PGA423 @ 1.75 V) 54.7 W (1.4 GHz 0.18 µm PGA423 @ 1.75 V) 57.8 W (1.5 GHz 0.18 µm PGA423 @ 1.75 V) 61.0 W (1.6 GHz 0.18 µm PGA423 @ 1.75 V) 64.0 W (1.7 GHz 0.18 µm PGA423 @ 1.75 V) 66.7 W (1.8 GHz 0.18 µm PGA423 @ 1.75 V) 69.2 W (1.9 GHz 0.18 µm PGA423 @ 1.75 V) 71.8 W (2.0 GHz 0.18 µm PGA423 @ 1.75 V) 55.3 W (1.4 GHz 0.18 µm µPGA478 @ 1.75 V) 57.9 W (1.5 GHz 0.18 µm µPGA478 @ 1.75 V) 60.8 W (1.6 GHz 0.18 µm µPGA478 @ 1.75 V) 63.5 W (1.7 GHz 0.18 µm µPGA478 @ 1.75 V) 66.1 W (1.8 GHz 0.18 µm µPGA478 @ 1.75 V) 72.8 W (1.9 GHz 0.18 µm µPGA478 @ 1.75 V) 75.3 W (2.0 GHz 0.18 µm µPGA478 @ 1.75 V) 52.8 W (2.0 GHz 0.13 µm µPGA478 @ 1.525 V with 128 KB L2) 55.5 W (2.1 GHz 0.13 µm µPGA478 @ 1.525 V with 128 KB L2) 57.1 W (2.2 GHz 0.13 µm µPGA478 @ 1.525 V with 128 KB L2) 58.3 W (2.3 GHz 0.13 µm µPGA478 @ 1.525 V with 128 KB L2) 59.8 W (2.4 GHz 0.13 µm µPGA478 @ 1.525 V with 128 KB L2) 61.0 W (2.5 GHz 0.13 µm µPGA478 @ 1.525 V with 128 KB L2) 62.6 W (2.6 GHz 0.13 µm µPGA478 @ 1.525 V with 128 KB L2) 73.0 W (2.40B GHz 0.09 µm µPGA478 @ 1.400 V with 256 KB L2) 73.0 W (2.53B GHz 0.09 µm µPGA478 @ 1.400 V with 256 KB L2) 73.0 W (2.66B GHz 0.09 µm µPGA478 @ 1.400 V with 256 KB L2) 73.0 W (2.80B GHz 0.09 µm µPGA478 @ 1.400 V with 256 KB L2) 38.7 W (1.6 GHz 0.13 µm µPGA478 @ 1.50 V, sub-45W) 41.6 W (1.8 GHz 0.13 µm µPGA478 @ 1.50 V, sub-45W) 44.6 W (2.0 GHz 0.13 µm µPGA478 @ 1.50 V, sub-45W) 52.4 W (2.0 GHz 0.13 µm µPGA478 @ 1.500 V) 55.1 W (2.2 GHz 0.13 µm µPGA478 @ 1.500 V) 57.8 W (2.4 GHz 0.13 µm µPGA478 @ 1.500 V) 59.3 W (2.5 GHz 0.13 µm µPGA478 @ 1.500 V) 54.3 W (2.0 GHz 0.13 µm µPGA478 @ 1.525 V) 57.1 W (2.2 GHz 0.13 µm µPGA478 @ 1.525 V) 59.8 W (2.4 GHz 0.13 µm µPGA478 @ 1.525 V) 61.0 W (2.5 GHz 0.13 µm µPGA478 @ 1.525 V) 62.6 W (2.6 GHz 0.13 µm µPGA478 @ 1.525 V) 66.8 W (2.7 GHz 0.13 µm µPGA478 @ 1.525 V) 68.4 W (2.8 GHz 0.13 µm µPGA478 @ 1.525 V) 56.0 W (2.26B GHz 0.13 µm µPGA478 @ 1.50 V) 57.8 W (2.40B GHz 0.13 µm µPGA478 @ 1.50 V) 59.3 W (2.53B GHz 0.13 µm µPGA478 @ 1.50 V) 58.0 W (2.26B GHz 0.13 µm µPGA478 @ 1.525 V) 59.8 W (2.40B GHz 0.13 µm µPGA478 @ 1.525 V) 61.5 W (2.53B GHz 0.13 µm µPGA478 @ 1.525 V) 66.1 W (2.66B GHz 0.13 µm µPGA478 @ 1.525 V) 68.4 W (2.80B GHz 0.13 µm µPGA478 @ 1.525 V) 70.0 W (3.06B GHz 0.13 µm µPGA478 @ 1.550 V) 76.0 W (3.20B GHz 0.13 µm µPGA478 @ 1.550 V) 81.8 W (3.06B GHz 0.13 µm µPGA478 @ 1.525 V with HTT) 66.2 W (2.4D GHz 0.13 µm µPGA478 @ 1.525 V with HTT) 69.0 W (2.6D GHz 0.13 µm µPGA478 @ 1.525 V with HTT) 69.7 W (2.8D GHz 0.13 µm µPGA478 @ 1.525 V with HTT) 81.9 W (3.0D GHz 0.13 µm µPGA478 @ 1.525 V with HTT) 82.0 W (3.2D GHz 0.13 µm µPGA478 @ 1.525 V with HTT) 89.0 W (3.4D GHz 0.13 µm µPGA478 @ 1.525 V with HTT) 92.1 W (3.2D GHz 0.13 µm µPGA478 @ 1.525 V with HTT and L3) 102.9 W (3.4D GHz 0.13 µm µPGA478 @ 1.525 V with HTT and L3) 109.6 W (3.4D GHz 0.13 µm LGA775 @ 1.600 V with HTT and L3) 89.0 W (2.80B GHz 0.09 µm µPGA478 @ 1.400 V) 89.0 W (2.8D GHz 0.09 µm µPGA478 @ 1.400 V with HTT) 89.0 W (3.0D GHz 0.09 µm µPGA478 @ 1.400 V with HTT) 103.0 W (3.2D GHz 0.09 µm µPGA478 @ 1.400 V with HTT) 103.0 W (3.4D GHz 0.09 µm µPGA478 @ 1.400 V with HTT) 84.0 W (2.80B GHz 0.09 µm LGA775 @ 1.425 V) 84.0 W (2.8D GHz 0.09 µm LGA775 @ 1.425 V with HTT) 84.0 W (3.0D GHz 0.09 µm LGA775 @ 1.425 V with HTT) 84.0 W (3.2D GHz 0.09 µm LGA775 @ 1.425 V with HTT) 115.0 W (3.4D GHz 0.09 µm LGA775 @ 1.425 V with HTT) 115.0 W (3.6D GHz 0.09 µm LGA775 @ 1.425 V with HTT) 56.0 W (1.4 GHz 0.18 µm PGA603 @ 1.70 V) 59.2 W (1.5 GHz 0.18 µm PGA603 @ 1.70 V) 65.8 W (1.7 GHz 0.18 µm PGA603 @ 1.70 V) 77.5 W (2.0 GHz 0.18 µm PGA603 @ 1.70 V) 65.0 W (1.4 GHz 0.18 µm PGA603 @ 1.70 V with L3 Cache) 68.0 W (1.5 GHz 0.18 µm PGA603 @ 1.70 V with L3 Cache) 72.0 W (1.6 GHz 0.18 µm PGA603 @ 1.70 V with L3 Cache) 55.0 W (1.8 GHz 0.13 µm PGA603 @ 1.50 V) 58.0 W (2.0 GHz 0.13 µm PGA603 @ 1.50 V) 61.0 W (2.2 GHz 0.13 µm PGA603 @ 1.50 V) 65.0 W (2.4 GHz 0.13 µm PGA603 @ 1.50 V) 71.0 W (2.6 GHz 0.13 µm PGA603 @ 1.50 V) 72.0 W (2.66 GHz 0.13 µm PGA603 @ 1.50 V) 74.0 W (2.8 GHz 0.13 µm PGA603 @ 1.50 V) 85.0 W (3.0 GHz 0.13 µm PGA603 @ 1.50 V) 85.0 W (3.06 GHz 0.13 µm PGA603 @ 1.50 V) 103.0 W (2.8D GHz 0.09 µm PGA603 @ 1.40 V) 103.0 W (3.0D GHz 0.09 µm PGA603 @ 1.40 V) 103.0 W (3.2D GHz 0.09 µm PGA603 @ 1.40 V) 103.0 W (3.4D GHz 0.09 µm PGA603 @ 1.40 V) 103.0 W (3.6D GHz 0.09 µm PGA603 @ 1.40 V) 54.0 W (1.5 GHz 0.13 µm PGA603 @ 1.475 V with L3 Cache) 63.0 W (1.9 GHz 0.13 µm PGA603 @ 1.475 V with L3 Cache) 65.0 W (2.0 GHz 0.13 µm PGA603 @ 1.475 V with L3 Cache) 74.0 W (2.5 GHz 0.13 µm PGA603 @ 1.475 V with L3 Cache) 83.0 W (2.8 GHz 0.13 µm PGA603 @ 1.475 V with L3 Cache) 74.0 W (2.2 GHz 0.13 µm PGA603 @ 1.475 V with L3 Cache 0F26h) 91.0 W (2.7 GHz 0.13 µm PGA603 @ 1.475 V with L3 Cache 0F26h) 97.0 W (3.0 GHz 0.13 µm PGA603 @ 1.475 V with L3 Cache 0F26h) 87.0 W (3.06B GHz 0.13 µm PGA603 @ 1.525 V with L3 Cache) 92.0 W (3.20B GHz 0.13 µm PGA603 @ 1.525 V with L3 Cache) 20.8 W (1.2 GHz 0.13 µm µFCPGA478 @ 1.2 V) 25.8 W (1.4 GHz 0.13 µm µFCPGA478 @ 1.3 V) 26.9 W (1.5 GHz 0.13 µm µFCPGA478 @ 1.3 V) 30.0 W (1.6 GHz 0.13 µm µFCPGA478 @ 1.3 V) 30.0 W (1.7 GHz 0.13 µm µFCPGA478 @ 1.3 V) 30.0 W (1.8 GHz 0.13 µm µFCPGA478 @ 1.3 V) 32.0 W (1.9 GHz 0.13 µm µFCPGA478 @ 1.3 V) 32.0 W (2.0 GHz 0.13 µm µFCPGA478 @ 1.3 V) 35.0 W (2.2 GHz 0.13 µm µFCPGA478 @ 1.3 V) 35.0 W (2.4 GHz 0.13 µm µFCPGA478 @ 1.3 V) 35.0 W (2.5 GHz 0.13 µm µFCPGA478 @ 1.3 V) 35.0 W (2.6 GHz 0.13 µm µFCPGA478 @ 1.3 V) 88.0 W (2.80B GHz 0.09 µm µFCPGA478 DTR @ 1.4 V) 88.0 W (3.06B GHz 0.09 µm µFCPGA478 DTR @ 1.4 V) 88.0 W (3.20B GHz 0.09 µm µFCPGA478 DTR @ 1.4 V) 20.8 W (1.2 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) 30.0 W (1.4 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) 30.0 W (1.5 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) 30.0 W (1.6 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) 30.0 W (1.7 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) 30.0 W (1.8 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) 32.0 W (2.0 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) 35.0 W (2.2 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) 35.0 W (2.4 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) 35.0 W (2.5 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) |
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| Maximum Power |
~66 W (1.3 GHz 0.18 µm PGA423 @ 1.70 V) ~71 W (1.4 GHz 0.18 µm PGA423 @ 1.70 V) ~75 W (1.5 GHz 0.18 µm PGA423 @ 1.70 V) ~70 W (1.3 GHz 0.18 µm PGA423 @ 1.75 V) ~74 W (1.4 GHz 0.18 µm PGA423 @ 1.75 V) ~79 W (1.5 GHz 0.18 µm PGA423 @ 1.75 V) ~83 W (1.6 GHz 0.18 µm PGA423 @ 1.75 V) ~87 W (1.7 GHz 0.18 µm PGA423 @ 1.75 V) ~88 W (1.8 GHz 0.18 µm PGA423 @ 1.75 V) ~92 W (1.9 GHz 0.18 µm PGA423 @ 1.75 V) ~96 W (2.0 GHz 0.18 µm PGA423 @ 1.75 V) ~72 W (1.4 GHz 0.18 µm µPGA478 @ 1.75 V) ~76 W (1.5 GHz 0.18 µm µPGA478 @ 1.75 V) ~80 W (1.6 GHz 0.18 µm µPGA478 @ 1.75 V) ~84 W (1.7 GHz 0.18 µm µPGA478 @ 1.75 V) ~88 W (1.8 GHz 0.18 µm µPGA478 @ 1.75 V) ~96 W (1.9 GHz 0.18 µm µPGA478 @ 1.75 V) ~100 W (2.0 GHz 0.18 µm µPGA478 @ 1.75 V) ~67 W (2.0 GHz 0.13 µm µPGA478 @ 1.525 V with 128 KB L2) ~70 W (2.1 GHz 0.13 µm µPGA478 @ 1.525 V with 128 KB L2) ~73 W (2.2 GHz 0.13 µm µPGA478 @ 1.525 V with 128 KB L2) ~75 W (2.3 GHz 0.13 µm µPGA478 @ 1.525 V with 128 KB L2) ~77 W (2.4 GHz 0.13 µm µPGA478 @ 1.525 V with 128 KB L2) ~79 W (2.5 GHz 0.13 µm µPGA478 @ 1.525 V with 128 KB L2) ~82 W (2.6 GHz 0.13 µm µPGA478 @ 1.525 V with 128 KB L2) ~94 W (2.40B GHz 0.09 µm µPGA478 @ 1.400 V with 256 KB L2) ~94 W (2.53B GHz 0.09 µm µPGA478 @ 1.400 V with 256 KB L2) ~94 W (2.66B GHz 0.09 µm µPGA478 @ 1.400 V with 256 KB L2) ~94 W (2.80B GHz 0.09 µm µPGA478 @ 1.400 V with 256 KB L2) ~49 W (1.6 GHz 0.13 µm µPGA478 @ 1.50 V, sub-45W) ~54 W (1.8 GHz 0.13 µm µPGA478 @ 1.50 V, sub-45W) ~58 W (2.0 GHz 0.13 µm µPGA478 @ 1.50 V, sub-45W) ~66 W (2.0 GHz 0.13 µm µPGA478 @ 1.500 V) ~71 W (2.2 GHz 0.13 µm µPGA478 @ 1.500 V) ~75 W (2.4 GHz 0.13 µm µPGA478 @ 1.500 V) ~77 W (2.5 GHz 0.13 µm µPGA478 @ 1.500 V) ~69 W (2.0 GHz 0.13 µm µPGA478 @ 1.525 V) ~73 W (2.2 GHz 0.13 µm µPGA478 @ 1.525 V) ~77 W (2.4 GHz 0.13 µm µPGA478 @ 1.525 V) ~79 W (2.5 GHz 0.13 µm µPGA478 @ 1.525 V) ~82 W (2.6 GHz 0.13 µm µPGA478 @ 1.525 V) ~83 W (2.7 GHz 0.13 µm µPGA478 @ 1.525 V) ~85 W (2.8 GHz 0.13 µm µPGA478 @ 1.525 V) ~72 W (2.26B GHz 0.13 µm µPGA478 @ 1.50 V) ~75 W (2.40B GHz 0.13 µm µPGA478 @ 1.50 V) ~77 W (2.53B GHz 0.13 µm µPGA478 @ 1.50 V) ~74 W (2.26B GHz 0.13 µm µPGA478 @ 1.525 V) ~77 W (2.40B GHz 0.13 µm µPGA478 @ 1.525 V) ~80 W (2.53B GHz 0.13 µm µPGA478 @ 1.525 V) ~82 W (2.66B GHz 0.13 µm µPGA478 @ 1.525 V) ~85 W (2.80B GHz 0.13 µm µPGA478 @ 1.525 V) ~101 W (3.06B GHz 0.13 µm µPGA478 @ 1.550 V) ~104 W (3.20B GHz 0.13 µm µPGA478 @ 1.550 V) ~100 W (3.06B GHz 0.13 µm µPGA478 @ 1.525 V with HTT) ~80 W (2.4D GHz 0.13 µm µPGA478 @ 1.525 V with HTT) ~84 W (2.6D GHz 0.13 µm µPGA478 @ 1.525 V with HTT) ~85 W (2.8D GHz 0.13 µm µPGA478 @ 1.525 V with HTT) ~99 W (3.0D GHz 0.13 µm µPGA478 @ 1.525 V with HTT) ~103 W (3.2D GHz 0.13 µm µPGA478 @ 1.525 V with HTT) ~109 W (3.4D GHz 0.13 µm µPGA478 @ 1.525 V with HTT) ~109 W (3.2D GHz 0.13 µm µPGA478 @ 1.525 V with HTT and L3) ~118 W (3.4D GHz 0.13 µm µPGA478 @ 1.525 V with HTT and L3) ~134 W (3.4D GHz 0.13 µm LGA775 @ 1.600 V with HTT and L3) ~109 W (2.80B GHz 0.09 µm µPGA478 @ 1.400 V) ~109 W (2.8D GHz 0.09 µm µPGA478 @ 1.400 V with HTT) ~109 W (3.0D GHz 0.09 µm µPGA478 @ 1.400 V with HTT) ~127 W (3.2D GHz 0.09 µm µPGA478 @ 1.400 V with HTT) ~127 W (3.4D GHz 0.09 µm µPGA478 @ 1.400 V with HTT) ~101 W (2.80B GHz 0.09 µm LGA775 @ 1.425 V) ~101 W (2.8D GHz 0.09 µm LGA775 @ 1.425 V with HTT) ~101 W (3.0D GHz 0.09 µm LGA775 @ 1.425 V with HTT) ~101 W (3.2D GHz 0.09 µm LGA775 @ 1.425 V with HTT) ~151 W (3.4D GHz 0.09 µm LGA775 @ 1.425 V with HTT) ~151 W (3.6D GHz 0.09 µm LGA775 @ 1.425 V with HTT) ~71 W (1.4 GHz 0.18 µm PGA603 @ 1.70 V) ~75 W (1.5 GHz 0.18 µm PGA603 @ 1.70 V) ~84 W (1.7 GHz 0.18 µm PGA603 @ 1.70 V) ~97 W (2.0 GHz 0.18 µm PGA603 @ 1.70 V) ~78 W (1.4 GHz 0.18 µm PGA603 @ 1.70 V with L3 Cache) ~82 W (1.5 GHz 0.18 µm PGA603 @ 1.70 V with L3 Cache) ~87 W (1.6 GHz 0.18 µm PGA603 @ 1.70 V with L3 Cache) ~62 W (1.8 GHz 0.13 µm PGA603 @ 1.50 V) ~66 W (2.0 GHz 0.13 µm PGA603 @ 1.50 V) ~70 W (2.2 GHz 0.13 µm PGA603 @ 1.50 V) ~74 W (2.4 GHz 0.13 µm PGA603 @ 1.50 V) ~82 W (2.6 GHz 0.13 µm PGA603 @ 1.50 V) ~83 W (2.66 GHz 0.13 µm PGA603 @ 1.50 V) ~86 W (2.8 GHz 0.13 µm PGA603 @ 1.50 V) ~101 W (3.0 GHz 0.13 µm PGA603 @ 1.50 V) ~101 W (3.06 GHz 0.13 µm PGA603 @ 1.50 V) ~125 W (2.8D GHz 0.09 µm PGA603 @ 1.40 V) ~125 W (3.0D GHz 0.09 µm PGA603 @ 1.40 V) ~125 W (3.2D GHz 0.09 µm PGA603 @ 1.40 V) ~125 W (3.4D GHz 0.09 µm PGA603 @ 1.40 V) ~125 W (3.6D GHz 0.09 µm PGA603 @ 1.40 V) ??? W (1.5 GHz 0.13 µm PGA603 @ 1.475 V with L3 Cache) ??? W (1.9 GHz 0.13 µm PGA603 @ 1.475 V with L3 Cache) ??? W (2.0 GHz 0.13 µm PGA603 @ 1.475 V with L3 Cache) ??? W (2.5 GHz 0.13 µm PGA603 @ 1.475 V with L3 Cache) ??? W (2.8 GHz 0.13 µm PGA603 @ 1.475 V with L3 Cache) ??? W (2.2 GHz 0.13 µm PGA603 @ 1.475 V with L3 Cache 0F26h) ??? W (2.7 GHz 0.13 µm PGA603 @ 1.475 V with L3 Cache 0F26h) ??? W (3.0 GHz 0.13 µm PGA603 @ 1.475 V with L3 Cache 0F26h) ~105 W (3.06B GHz 0.13 µm PGA603 @ 1.525 V with L3 Cache) ~114 W (3.20B GHz 0.13 µm PGA603 @ 1.525 V with L3 Cache) ~26 W (1.2 GHz 0.13 µm µFCPGA478 @ 1.2 V) ~34 W (1.4 GHz 0.13 µm µFCPGA478 @ 1.3 V) ~36 W (1.5 GHz 0.13 µm µFCPGA478 @ 1.3 V) ~37 W (1.6 GHz 0.13 µm µFCPGA478 @ 1.3 V) ~39 W (1.7 GHz 0.13 µm µFCPGA478 @ 1.3 V) ~40 W (1.8 GHz 0.13 µm µFCPGA478 @ 1.3 V) ~42 W (1.9 GHz 0.13 µm µFCPGA478 @ 1.3 V) ~43 W (2.0 GHz 0.13 µm µFCPGA478 @ 1.3 V) ~45 W (2.2 GHz 0.13 µm µFCPGA478 @ 1.3 V) ~48 W (2.4 GHz 0.13 µm µFCPGA478 @ 1.3 V) ~49 W (2.5 GHz 0.13 µm µFCPGA478 @ 1.3 V) ~50 W (2.6 GHz 0.13 µm µFCPGA478 @ 1.3 V) ~112 W (2.80B GHz 0.09 µm µFCPGA478 DTR @ 1.4 V) ~112 W (3.06B GHz 0.09 µm µFCPGA478 DTR @ 1.4 V) ~112 W (3.20B GHz 0.09 µm µFCPGA478 DTR @ 1.4 V) ~30 W (1.2 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) ~34 W (1.4 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) ~36 W (1.5 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) ~37 W (1.6 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) ~39 W (1.7 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) ~40 W (1.8 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) ~43 W (2.0 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) ~45 W (2.2 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) ~48 W (2.4 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) ~49 W (2.5 GHz 0.13 µm µFCPGA478 mobile Celeron @ 1.3 V) |
||
| Cooling | Required | ||
| Clock Frequencies | CPU Core Speed |
1.3...2.0 GHz (PGA423) 1.4...2.0 GHz (µPGA478, 0.18 µm) 1.7...1.8 GHz (µPGA478, 0.18 µm Celeron) 2.0...2.8 GHz (µPGA478, 0.13 µm Celeron) 2.40B...2.80B GHz (µPGA478, 0.09 µm Celeron) 1.6, 1.8, 2.0, 2.2, and 2.4...2.6 GHz (µPGA478, 0.13 µm) 2.26B, 2.40B, 2.53B, 2.66B, 2.80B GHz (µPGA478, 0.13 µm) 2.80B (µPGA478, 0.09 µm) 2.80B (LGA775, 0.09 µm) 3.06B GHz (µPGA478, 0.13 µm HTT) 2.4D, 2.6D, 2.8D, 3.0D, 3.2D, 3.4D GHz (µPGA478, 0.13 µm HTT) 2.8D, 3.0D, 3.2D, 3.4D (µPGA478, 0.09 µm HTT) 2.8D, 3.0D, 3.2D, 3.4D, 3.6D (LGA775, 0.09 µm HTT) 3.2D and 3.4D GHz (µPGA478, 0.13 µm HTT with L3 Cache) 3.4D GHz (LGA775, 0.13 µm HTT with L3 Cache) 1.4, 1.5, 1.7, 2.0 GHz (PGA603, 0.18 µm) 1.4, 1.5, 1.6 GHz (PGA603, 0.18 µm with L3 Cache) 1.8, 2.0, 2.2, 2.4, 2.6, 2.8, 3.0 GHz (PGA603, 0.13 µm) 2.0B, 2.4B, 2.66B, 2.8B, 3.06B GHz (PGA603, 0.13 µm) 2.8D, 3.0D, 3.2D, 3.4D, 3.6D GHz (PGA603, 0.09 µm) 3.06B and 3.2B GHz (PGA603, 0.13 µm with L3 Cache) 1.5, 1.9, 2.0, 2.5 GHz (PGA603, 0.13 µm with 1024 KB L3 Cache) 2.0, 2.2, 2.7, 2.8 GHz (PGA603, 0.13 µm with 2048 KB L3 Cache) 3.0 GHz (PGA603, 0.13 µm with 4096 KB L3 Cache) 1.4...2.0/1.2, 2.2/1.2, 2.4...2.6/1.2 GHz (µFCPGA478, 0.13 µm*) 2.40B,2.66B,2.80B,3.06B/1.20B GHz (µFCPGA478, 0.13 µm*) 2.66B,2.80B,3.06B,3.20B/1.60B GHz (µFCPGA478, 0.13 µm HTT*) 1.4...1.8, 2.0, 2.2, 2.4, 2.5 GHz (µFCPGA478, 0.13 µm mob. Celeron) 1.2 GHz (µFCPGA478, 0.13 µm embedded Celeron) 2.80B, 3.06B, 3.20B (µFCPGA478, 0.09 µm HTT DTR) * with SpeedStep Technology |
|
| L1 Cache Speed | 1.0x Core Speed | ||
| L2 Cache Speed | 1.0x Core Speed | ||
| L3 Cache Speed | 1.0x Core Speed | ||
| External Bus Speed |
100 MHz Quad-Pumped 133 MHz Quad-Pumped (aka B) 200 MHz Quad-Pumped (aka D) 266 MHz Quad-Pumped (aka F) AGTL+ with VTT = VCC up to 12 Outstanding Transactions |
||
| Core/Bus Ratio | 13.0x, 14.0x, ..., 30.0x | ||
| Miscellaneous | usual Motherboard |
Single Processor PGA423 Single Processor µPGA478 Single Processor LGA775 Single, Dual, or Quad Processor PGA603 |
|
| usual Chipset | Intel | ||
| Pictures |
0.18 µm Die (180 KB JPG) 0.18 µm Die (60 KB JPG) -- 1 MB L3 Cache 0.13 µm Die (293 KB JPG) 0.09 µm Die (312 KB JPG) -- 1 MB L2 Cache 0.09 µm Die (406 KB JPG) -- 1 MB L2 Cache DC 0.09 µm Die (244 KB JPG) -- 2 MB L2 Cache 65 nm Die (186 KB JPG) -- 2 MB L2 Cache SC 65 nm Die (297 KB JPG) -- 2 MB L2 Cache DC 65 nm Die (106 KB JPG) -- 1 MB L2 Cache DC 16 MB L3 Cache 65 nm Die (102 KB JPG) -- 1 MB L2 Cache DC 16 MB L3 Cache 0.13 µm 200 mm Wafer (257 KB JPG) 0.13 µm 200 mm Wafer (223 KB JPG) -- 4 MB L3 Cache 0.13 µm 300 mm Wafer (484 KB JPG) 0.09 µm 300 mm Wafer (468 KB JPG) -- 2 MB L2 Cache PGA423 (215 KB JPG) µPGA478 (102 KB JPG) µPGA478EE (95 KB JPG) µPGA478 0.09 µm (88 KB JPG) LGA775 0.09 µm (126 KB JPG) LGA775 Socket (222 KB JPG) PGA603 0.18 µm (101 KB JPG) PGA603 0.18 µm MP (99 KB JPG) PGA603 0.13 µm (61 KB JPG) PGA603 0.13 µm MP (47 KB JPG) PGA603 0.09 µm (139 KB JPG) PGA603 0.09 µm MP (35 KB JPG) µFCPGA478 (70 KB JPG) |
||
| Processor Core | Generic Details | RISC, Out-of-order and Speculative Execution | |
| Specific Details |
up to 126 µOPs In-flight, split into 2x 63 if HTT is active up to 48 Loads In-flight, split into 2x 24 if HTT is active up to 24 Stores In-Flight, split into 2x 12 if HTT is active (0.18 µm) up to 24 Stores In-Flight, split into 2x 12 if HTT is active (0.13 µm) up to 32 Stores In-Flight, split into 2x 16 if HTT is active (0.09 µm) up to 32 Stores In-Flight, split into 2x 16 if HTT is active (65 nm) |
||
| Registers |
32 Bit Integer, 80 Bit FP, 64 Bit MM, 128 Bit XMM 128 Entry Integer Register File 128 Entry FP Register File |
||
| Pipeline Depth |
20 Stages (excludes ??? Decode Stages before TC, 0.18 µm) 20 Stages (excludes ??? Decode Stages before TC, 0.13 µm) 31 Stages (excludes ??? Decode Stages before TC, 0.09 µm) 31 Stages (excludes ??? Decode Stages before TC, 65 nm) |
||
| Instruction Decode | 1x IA-32/Cycle | ||
| Instruction Dispatch |
6x µOPs/Cycle 3x µOPs/Cycle Limit imposed by Trace Cache |
||
| Execution Units |
Port 0: ALU *, FP Move/Store/FXCH, Branch, Store Data Port 1: ALU *, Slow ALU (Mul/Shift/Rotate) **, FP Execute *** Port 2: Load, Prefetch Port 3: Store Address * Double-pumped, ** 0.09 µm and 65 nm: Dedicated IMUL and Double-Pumped Shift/Rotate *** FP Add, FP Mul, FP Div/Sqrt, MM ALU, MM Shift/Rotate/Shuffle/Pack/Unpack, MM Misc |
||
| Execution Speed | up to 6 µOPs/Cycle | ||
| Instruction Retirement | 3x µOPs/Cycle | ||
| Processor Buses | Address Bus Width |
36 Bit 40 Bit (0.09 µm and 65 nm Xeon MP) |
|
| Data Bus Width | 64 Bit | ||
| Physical Memory |
2^36 Bit = 64 GB 2^40 Bit = 1 TB (0.09 µm and 65 nm Xeon MP) |
||
| Virtual Memory |
IA-32: 2^32 Bit = 4 GB EM64T: 2^48 Bit = 256 TB |
||
| Logical Memory |
IA-32: (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB) EM64T: n/a |
||
| Multithreading | SMT, using Hyper-Threading Technology | ||
| Multiprocessing | SMP, using integrated local xAPICs | ||
| Power Management |
HLT, STPCLK, SMI/SMM, Sleep, Deep Sleep Automatic Clock Throttling prevents Overheating SpeedStep Technology (mobile parts) |
||
| Processor Caches | Level 0 | N/A | |
| Level 1 | Code |
12 K µOP Trace Cache, 8-Way, 6 µOPs/Line, microcode is inserted both into and after TC, the built traces span accross taken branches, indirect branches can go into the TC (0.09 µm), indirect branches can go into the TC (65 nm), SW prefetches can go into the TC (0.09 µm), SW prefetches can go into the TC (65 nm), SMC on 1 KB Fetch or 2 KB Write granularity flushes the entire TC |
|
|
Data (0.18 µm) Data (0.13 µm) |
8 KB, 4-Way, 64 Byte/Line, MESI, 1 Line/Sector, Write-Through, Pseudo-LRU, Non-blocking (up to 4 Load Misses), Virtually Addressed, Physically Tagged, Alias Conflicts for VA Bits 31...16 (> wpTAG), Alias Conflicts for VA Bits 31...20 (> dTAG), Dual-ported (1 Load and 1 Store), 2/9 Cycle Latency (Integer/FP), 16 Byte Path to FP Unit for Loads |
||
|
Data (0.09 µm) Data (65 nm) |
16 KB, 8-Way, 64 Byte/Line, MESI, 1 Line/Sector, Write-Through, Pseudo-LRU, Non-blocking (up to 8 Load Misses), Virtually Addressed, Physically Tagged, Alias Conflicts for VA Bits 47...22 (> wpTAG), Dual-ported (1 Load and 1 Store), 4/12 Cycle Latency (Integer/FP), 16 Byte Path to FP Unit for Loads |
||
| Level 2 | Unified (0.18 µm) Celeron |
128 KB, 4-Way, 64 Byte/Line, MESI, 2 Lines/Sector, Exclusive, Pseudo-LRU, Non-blocking, 64 GB cacheable, Alias Conflicts for VA Bits 31...24 (> µTLB), Alias Conflicts for PA Bits 35...24 (> wpTAG), 7/7 Cycle Latency (Integer/FP), 256 Bit Bus, Data on every Cycle |
|
| Unified (0.18 µm) non-Celeron |
256 KB, 8-Way, 64 Byte/Line, MESI, 2 Lines/Sector, Exclusive, Pseudo-LRU, Non-blocking, 64 GB cacheable, Alias Conflicts for VA Bits 31...24 (> µTLB), Alias Conflicts for PA Bits 35...24 (> wpTAG), 7/7 Cycle Latency (Integer/FP), 256 Bit Bus, Data on every Cycle |
||
| Unified (0.13 µm) Celeron |
128 KB, 2-Way, 64 Byte/Line, MESI, 2 Lines/Sector, Exclusive, Pseudo-LRU, Alias Conflicts for VA Bits 31...24 (> µTLB), Non-blocking, 64 GB cacheable, 7/7 Cycle Latency (Integer/FP), 256 Bit Bus, Data on every Cycle |
||
| Unified (0.13 µm) mobile Celeron |
256 KB, 4-Way, 64 Byte/Line, MESI, 2 Lines/Sector, Exclusive, Pseudo-LRU, Alias Conflicts for VA Bits 31...24 (> µTLB), Non-blocking, 64 GB cacheable, 7/7 Cycle Latency (Integer/FP), 256 Bit Bus, Data on every Cycle |
||
| Unified (0.13 µm) non-Celeron |
512 KB, 8-Way, 64 Byte/Line, MESI, 2 Lines/Sector, Exclusive, Pseudo-LRU, Alias Conflicts for VA Bits 31...24 (> µTLB), Non-blocking, 64 GB cacheable, 7/7 Cycle Latency (Integer/FP), 256 Bit Bus, Data on every Cycle |
||
| Unified (0.09 µm) Celeron |
256 KB, 4-Way, 64 Byte/Line, MESI, 2 Lines/Sector, Exclusive, Pseudo-LRU, Non-blocking, 64 GB cacheable, 18/18 Cycle Latency (Integer/FP), 256 Bit Bus, Data on every Cycle |
||
| Unified (0.09 µm) Unified (65 nm) non-Celeron |
1024 KB, 8-Way, 64 Byte/Line, MESI, 2 Lines/Sector, Exclusive, Pseudo-LRU, Non-blocking, 64 GB cacheable, 18/18 Cycle Latency (Integer/FP), 256 Bit Bus, Data on every Cycle |
||
| Unified (0.09 µm) Unified (65 nm) non-Celeron |
2048 KB, 8-Way, 64 Byte/Line, MESI, 2 Lines/Sector, Exclusive, Pseudo-LRU, Non-blocking, 64 GB cacheable, 20/20 Cycle Latency (Integer/FP), 256 Bit Bus, Data on every Cycle |
||
| Level 3 (selected parts) | Unified (0.18 µm) |
512 KB, 4-Way, 64 Byte/Line, MESI, 1024 KB, 8-Way, 64 Byte/Line, MESI, 2 Lines/Sector, Inclusive, Pseudo-LRU, Non-blocking, 64 GB cacheable, 14/14 Cycle Latency (Integer/FP) |
|
| Unified (0.13 µm) |
1024 KB, 8-Way, 64 Byte/Line, MESI, 2048 KB, 8-Way, 64 Byte/Line, MESI, 4096 KB, 8-Way, 64 Byte/Line, MESI, 2 Lines/Sector, Inclusive, Pseudo-LRU, Non-blocking, 64 GB cacheable, 14/14 Cycle Latency (Integer/FP) |
||
| Unified (0.09 µm) |
4096 KB, 8-Way, 64 Byte/Line, MESI, 8192 KB, 8-Way, 64 Byte/Line, MESI, 2 Lines/Sector, Inclusive, Pseudo-LRU, Non-blocking, 64 GB cacheable, ???/??? Cycle Latency (Integer/FP) |
||
| Unified (65 nm) |
4196 KB, 16-Way, 64 Byte/Line, MESI, 8192 KB, 16-Way, 64 Byte/Line, MESI, 16384 KB, 16-Way, 64 Byte/Line, MESI, 2 Lines/Sector, Inclusive, Pseudo-LRU, Non-blocking, 64 GB cacheable, Shared, ???/??? Cycle Latency (Integer/FP) 256x 64 KB Storage Arrays 32x 68 KB Redundancy Arrays |
||
| Processor Buffers | Fill Buffer |
4x 64 Byte (0.18 µm) 4x 64 Byte (0.13 µm) 8x 64 Byte (0.09 µm) 8x 64 Byte (65 nm) |
|
| WC Buffer |
6x 64 Byte (0.18 µm) 6x 64 Byte (0.13 µm) 8x 64 Byte (0.09 µm) 8x 64 Byte (65 nm) |
||
| Code Prefetch | 64 Byte, filled 32 Byte at a Time | ||
| Data Prefetch |
up to 256 Bytes ahead, fills one way of the L2 (but not the L1) Cache, 1 Stream per 4 KB Page (Load or Store), up to 8 Streams at a Time, never crosses 4 KB Page Boundary unless there are Demand Loads, 0.09 µm: up to 512 Bytes ahead, Specul. TLB Fills & Page Crossing 65 nm: up to 512 Bytes ahead, Specul. TLB Fills & Page Crossing |
||
| Branch Prediction | Static | Yes | |
| Dynamic iTLB BTB |
4,096 Entries, ???-Way, providing 16x 4-State Pattern Recognition Indirect Branch Prediction (0.09 µm) Indirect Branch Prediction (65 nm) |
||
| Trace Cache BTB |
512 Entries, ???-Way (0.18 µm) 512 Entries, ???-Way (0.13 µm) 2,048 Entries, ???-Way (0.09 µm) 2,048 Entries, ???-Way (65 nm) |
||
| SW Hints | on Conditional Branches: Taken, Not Taken | ||
| RSB | 16 Entries | ||
| TLB | 4 KB Code |
128 Entries, Full, ??? split into 2x 64 Entries if HTT is enabled |
|
| Large Code | N/A (uses 4 KB Code Entries) | ||
| Data | 64 Entries, Full, ???, Dual-ported | ||
|
µTLB for L2 Cache (0.18 µm and 0.13 µm) |
64 Entries, 4-Way, ???, Single-Ported see L2 Cache for VA and PA Tag Details |
||
| Instruction Set | Regular | IA-32, EM64T (0.09 µm) | |
| Floating Point | Integrated | ||
| Multi Media | MMX, SSE, SSE2, SSE3 (0.09 µm) | ||
| Processor Modes | Real, Protected, Virtual, Paging, SMM, Probe Mode | ||
