NexGen Nx686
| General Details | Name | Nx686 | |
| Codename | HA | ||
| Family/Generation | 80386, 6th Generation | ||
| Vendor | NexGen | ||
| Manufacturer | IBM | ||
| First Introduction |
Oct 10, 1995 (samples) Apr 2, 1997 (as AMD K6) |
||
| Physical Details | Package Type | 463 Pin PGA | |
| Package Size | 5.00 cm x 5.00 cm | ||
| Socket or Slot | Proprietary Socket | ||
| Transistors | 6,000,000 (includes 54 KB L1 Cache) | ||
| Process Technology |
5M, 0.44 µm, CMOS (samples) 5M, 0.35 µm, CMOS (target) |
||
| Die Size | ~180 mm² (0.44 µm) | ||
| Electrical Details | Split Voltage | Yes | |
| Core Voltage | 2.5 V | ||
| I/O Voltage | 3.3 V | ||
| Typical Power | ~4 W | ||
| Maximum Power | ~10 W | ||
| Cooling | Required | ||
| Clock Frequencies | CPU Core Speed | 180 MHz (samples) | |
| L1 Cache Speed | 2.0x Core Speed | ||
| L2 Cache Speed | 1.0x Core or External Bus Speed | ||
| External Bus Speed | 60 MHz (samples) | ||
| Core/Bus Ratio | 3.0x | ||
| Miscellaneous | usual Motherboard | Single Processor NexGen PCI | |
| usual Chipset | NexGen NxPCI | ||
| Pictures |
Nx686 Top (75 KB JPG) and Bottom (142 KB JPG) Nx686 Top (77 KB JPG) and Bottom (145 KB JPG) |
||
| Processor Core | Generic Details | RISC, Out-of-order and Speculative Execution | |
| Specific Details | 24 Entry ICU (up to 12 IA-32 instructions) | ||
| Registers | 32 Bit Integer, 80 Bit FP, ??? Bit MM, 48 Entry RAT | ||
| Pipeline Depth | 6 | ||
| Instruction Decoder |
1-2x IA-32/Cycle 1-4x ROPs/Cycle |
||
| Execution Units | Simple ALU, Complex ALU, MM, Load, Store, Branch, Non-pipelined FPU | ||
| Execution Speed | up to 6x ROPs/Cycle | ||
| Processor Buses | Address Bus Width | 32 Bit | |
| Data Bus Width | 64 Bit, separate 64 Bit Backside L2 Cache Bus | ||
| Physical Memory | 2^32 Bit = 4 GB | ||
| Virtual Memory | 2^32 Bit = 4 GB | ||
| Logical Memory | (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB) | ||
| Multiprocessing | N/A | ||
| Power Management | HLT, STPCLK, SMI/NexGen SMM | ||
| Processor Caches | Level 0 | N/A | |
| Level 1 | Code |
16 KB, 2-Way, 32 Byte/Line, SI, 3 Pre-decode Bits/Byte (adds 6 KB), LRU |
|
| Data |
32 KB, 2-Way, 32 Byte/Line, MESI, Dual-ported, LRU |
||
| Level 2 | Unified |
On-chip Controller for 256 KB ... 2 MB, WB, Direct Mapped, 32 Byte/Line, Single-ported, MESI, Separate SRAMs for Data and Tags |
|
| Processor Buffers | Read Buffer | ??? | |
| Write Buffer | ??? | ||
| Prefetch Queue | ??? | ||
| Branch Prediction | Static | Yes | |
| Dynamic | 8,192 Entries, 2-Level | ||
| BTC | 16 Entries, 16 Byte/Entry | ||
| RSB | 16 Entries, ??? Byte/Entry | ||
| TLB | Code | 64 Entries, ???, LRU | |
| Data | 128 Entries, ???, LRU | ||
| Instruction Set | Regular | IA-32 | |
| Floating Point | Integrated | ||
| Multi Media | MM | ||
| Processor Modes | Real, Protected, Virtual, Paging, SMM | ||
| Note: The NexGen Nx686 processor never made it beyond sampling. After its announcement at the 1995 Microprocessor forum, AMD aquired NexGen, and turned the Nx686 design into what is now known as the AMD K6 processor. The information above is based on articles which discussed the NexGen Nx686 design, and on AMD K6 processor details. |
