NexGen Nx586 and Nx586FP
| General Details | Name | Nx586, Nx586FP | |
| Codename | Nx586, Nx586FP | ||
| Family/Generation | 80386, 5th Generation | ||
| Vendor | NexGen | ||
| Manufacturer | IBM | ||
| First Introduction |
Mar ???, 1994 (Nx586 0.50 µm) Mar 10, 1995 (Nx586 0.44 µm) Nov ???, 1995 (Nx586FP) |
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| Physical Details | Package Type |
463 Pin PGA 463 Pin Multi-Chip Module PGA (CPU and FPU) |
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| Package Size | 5.00 cm x 5.00 cm | ||
| Socket or Slot | Proprietary Socket | ||
| Transistors | 3,500,000 (includes 2x 16 KB L1 Cache) | ||
| Process Technology |
4M, 0.50 µm, CMOS 5M, 0.44 µm, CMOS |
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| Die Size |
165 mm² (0.50 µm) 118 mm² (0.44 µm CPU die) 36 mm² (0.44 µm FPU die) |
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| Electrical Details | Split Voltage | N/A | |
| Core Voltage | 4.0 V | ||
| I/O Voltage | 4.0 V | ||
| Typical Power | ??? | ||
| Maximum Power | ??? | ||
| Cooling | Required | ||
| Clock Frequencies | CPU Core Speed |
PR75: 70/35 MHz PR80: 75/37.5 MHz PR90: 84/42 MHz PR100: 93/46.5 MHz PR110: 102/51 MHz PR120: 111/55.5 MHz |
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| L1 Cache Speed | 2.0x Core Speed | ||
| L2 Cache Speed | 1.0x External Bus Speed | ||
| External Bus Speed | 35, 37.5, 42, 46.5, 51, 55.5 MHz | ||
| Core/Bus Ratio | 2.0x | ||
| Miscellaneous | usual Motherboard | Single Processor NexGen VLB or PCI | |
| usual Chipset | NexGen NxVL or NxPCI | ||
| Pictures |
0.50 µm Die (111 KB JPG) Nx586 Top (74 KB JPG) and Bottom (131 KB JPG) Nx586FP Top (84 KB JPG) and Bottom (124 KB JPG) |
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| Processor Core | Generic Details | RISC, Out-of-order and Speculative Execution | |
| Specific Details | 14 Entry ROP Queue/Unit | ||
| Registers | 32 Bit Integer, 80 Bit FP, 22 Entry RAT | ||
| Pipeline Depth | 7 | ||
| Instruction Decoder | 1x IA-32/Cycle | ||
| Execution Units | Simple Integer, Complex Integer, Address, Non-pipelined FPU (Nx586FP) | ||
| Execution Speed |
up to 2x ROPs/Cycle (Nx586) up to 3x ROPs/Cycle (Nx586FP) |
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| Processor Buses | Address Bus Width | 32 Bit | |
| Data Bus Width | 64 Bit | ||
| Physical Memory | 2^32 Bit = 4 GB | ||
| Virtual Memory | 2^32 Bit = 4 GB | ||
| Logical Memory | (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB) | ||
| Multiprocessing | N/A | ||
| Power Management | N/A | ||
| Processor Caches | Level 0 | N/A | |
| Level 1 | Code |
16 KB, 4-Way, 32 Byte/Line, Dual-ported, SI, LRU |
|
| Data |
16 KB, 4-Way, 32 Byte/Line, Dual-ported, MESI, LRU |
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| Level 2 | Unified |
On-chip Controller for 256 KB or 1 MB, 4-Way, 32 Byte/Line, Single-ported, MESI, SRAMs Contain Tags and Microcode Update |
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| Processor Buffers | Read Buffer | ??? | |
| Write Buffer | 8 Entry Write Reservation Station | ||
| Prefetch Queue | 24 Byte | ||
| Branch Prediction | Static | Yes | |
| Dynamic | 2,048 Entries, 2-Level | ||
| BTC | 96 Entries, 24 Byte/Entry | ||
| RSB | 8 Entries, 24 Byte/Entry | ||
| TLB | Unified | 32 Entries, ???, LRU | |
| Instruction Set | Regular | IA-32 | |
| Floating Point | N/A (Nx586), Integrated (Nx586FP) | ||
| Multi Media | N/A | ||
| Processor Modes | Real, Protected, Virtual, Paging | ||
