IA-32 implementation
Cyrix M2 (6x86MX and M-II)




General Details Name 6x86MX (PR166..266), M-II (PR300..433)
Codename M2
Family/Generation 80586, 5th Generation, MMX
Vendor Cyrix
Manufacturer IBM, SGS, NS
First Introduction May 30, 1997 (PR166, PR200, and PR233)
Feb 16, 1998 (PR266)
Apr 14, 1998 (PR300)
Jun 15, 1998 (PR333)
Mar ???, 1999 (PR366)
Jul ???, 1999 (PR400 and PR433)
Physical Details Package Type 296 Pin PGA
Package Size 4.95 cm x 4.95 cm (PGA)
Socket or Slot Socket 7
Transistors 6,500,000 (includes 64 KB L1 Cache)
Process Technology 5M, 0.35 µm, CMOS
Die Size 197 mm² (CMOS 5x2)
156 mm² (CMOS 5x9)
119 mm² (CMOS 6S2)
65 mm² (CMOS 6x3)
Electrical Details Split Voltage Yes (determined via Motherboard)
Core Voltage 2.9 V (PR366 and lower)
2.2 V (PR366 and higher)
I/O Voltage 3.3 V
Typical Power 133 MHz: 10.6 W
150 MHz: 11.4 W
166 MHz: 11.5 W
187.5 MHz: 13.1 W
200 MHz: 13.5 W
207.5 MHz: 13.8 W
225 MHz: 15.0 W
233 MHz: 15.4 W (Wire Bond)
233 MHz: 16.9 W (C4 Flip-Chip)
250 MHz: 16.6 W (Wire Bond)
250 MHz: 18.3 W (C4 Flip-Chip)
250 MHz: 14.0 W (NS 2.9V)
250 MHz: 7.7 W (NS 2.2V)
285 MHz: 11.1 W (NS 2.2V)
300 MHz: 12.0 W (NS 2.2V)
Maximum Power 133 MHz: 17.6 W
150 MHz: 18.9 W
166 MHz: 19.1 W (Cyrix), 18.1 W (IBM)
187.5 MHz: 21.7 W (Cyrix), 19.7 W (IBM)
200 MHz: 22.3 W (Cyrix), 20.5 W (IBM)
207.5 MHz: 23.0 W (Cyrix), 21.3 W (IBM)
225 MHz: 24.9 W (Cyrix), 22.3 W (IBM)
233 MHz: 25.5 W (Cyrix), 22.8 W (IBM Wire Bond)
233 MHz: 27.0 W (IBM C4 Flip-Chip)
250 MHz: 27.6 W (Cyrix), 23.9 W (IBM Wire Bond)
250 MHz: 27.9 W (IBM C4 Flip-Chip)
250 MHz: 23.3 W (NS 2.9V)
250 MHz: 8.8 W (NS 2.2V)
285 MHz: 12.5 W (NS 2.2V)
300 MHz: 13.7 W (NS 2.2V)
Cooling Required
Clock Frequencies CPU Core Speed PR133: 100/50, 110/55
PR150: 120/60, 125/50
PR166: 133/66, 137.5/55, 150/50, 150/60
PR200: 150/75, 165/55, 166/66, 180/60
PR233: 166/83, 187.5/75, 200/66
PR266: 207.5/83, 225/75 (6x86MX), 233/66 (6x86MX)
PR300: 225/75 (M-II), 233/66 (M-II)
PR333: 250/83
PR366: 250/100
PR400: 285/95
PR433: 300/100
L1 Cache Speed 1.0x Core Speed
L2 Cache Speed 1.0x External Bus Speed
External Bus Speed 50, 55, 60, 66, 75, 83, 95 or 100 MHz
Core/Bus Ratio 2.0x, 2.5x, 3.0x, 3.5x
Miscellaneous usual Motherboard Single Processor Socket 7
usual Chipset Intel 82430FX, 82430HX, 82430VX, 82430TX, or non-Intel
Pictures 0.35 µm Die (162 KB JPG)
0.35 µm and 0.25 µm Open Packages (332 KB JPG)
ID=02h Top (73 KB JPG) and Bottom (100 KB JPG)
ID=04h Top (79 KB JPG) and Bottom (106 KB JPG)
ID=08h Top (66 KB JPG) and Bottom (101 KB JPG)
Processor Core Generic Details CISC, In-/Out-of-order and Pipelined Execution
Specific Details Dual Pipeline Design
Registers 32 Bit Integer, 80 Bit FP, 64 Bit MM, 32 Entry RAT
Pipeline Depth 1 (Shared) plus
2x 4+2 In-/Out-of-order (Dual Pipeline) Stages,
4x FP plus 6x FP Store Queue
Instruction Decoder 2x IA-32/Cycle
Execution Units 2x Integer, MMX, Non-pipelined FPU
Execution Speed up to 2x IA-32/Cycle
Processor Buses Address Bus Width 32 Bit
Data Bus Width 64 Bit
Physical Memory 2^32 Bit = 4 GB
Virtual Memory 2^32 Bit = 4 GB
Logical Memory (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB)
Multiprocessing N/A
Power Management HLT, STPCLK, SMI/SMM/Cyrix SMM, Suspend
Processor Caches Level 0 256 Byte, Full, 32 Byte/Line, LRU
Level 1 Unified 64 KB, 4-Way, 32 Byte/Line,
Dual-ported, Write Allocate, LRU
Level 2 Unified External, depends on Motherboard
Processor Buffers Read Buffer ???
Write Buffer ???
Prefetch Queue 64 Byte
Branch Prediction Static Yes
Dynamic 512 Entries, 4-Way, 4-State
RSB 8 Entries
TLB L1 16 Entries, Direct, LRU
Dual-Ported (Code/Data)
L2 384 Entries, 6-Way, LRU
Dual-ported (Code/Data)
Instruction Set Regular IA-32
Floating Point Integrated
Multi Media MMX, Cyrix extended MMX
Processor Modes Real, Protected, Virtual, Paging, SMM



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