Cyrix M1 (6x86, 6x86L, and 6x86LV)
| General Details | Name | 6x86, 6x86L, 6x86LV | |
| Codename |
M1 (6x86 using 3M Process) M1R (6x86 using 5M Process) M1L (6x86L) M1LV (6x86L) |
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| Family/Generation | 80586, 5th Generation | ||
| Vendor | Cyrix | ||
| Manufacturer | IBM, SGS, NS | ||
| First Introduction |
Feb 5, 1996 (PR133, PR150, and PR166) Jun 3, 1996 (PR200) |
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| Physical Details | Package Type |
296 Pin PGA (6x86 and 6x86L) 296 Pin PPGA (6x86L) |
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| Package Size |
4.95 cm x 4.95 cm (PGA) 4.95 cm x 4.95 cm (PPGA) |
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| Socket or Slot | Socket 5 or 7 | ||
| Transistors | 3,000,000 (includes 16 KB L1 Cache) | ||
| Process Technology |
3M, 0.65 µm, CMOS 5M, 0.65 µm, CMOS 5M, 0.35 µm, CMOS |
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| Die Size |
394 mm² (3M 0.65 µm) 225 mm² (5M 0.65 µm) 169 mm² (5M 0.35 µm) |
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| Electrical Details | Split Voltage |
N/A (6x86) Yes (6x86L, determined via Motherboard) |
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| Core Voltage |
3.52 V (6x86) 2.8 V (6x86L) 2.45 V (6x86LV) |
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| I/O Voltage |
3.52 V (6x86) 3.3 V (6x86L) 3.3 V (6x86LV) |
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| Typical Power |
80 MHz: 12.9 W (6x86) 100 MHz: 14.9 W (6x86) 110 MHz: 15.8 W (6x86) 120 MHz: 16.8 W (6x86) 133 MHz: 18.2 W (6x86) 150 MHz: 20.8 W (6x86) 100 MHz: 11.1 W (6x86L) 110 MHz: 11.7 W (6x86L) 120 MHz: 12.6 W (6x86L) 133 MHz: 13.4 W (6x86L) 150 MHz: 14.3 W (6x86L) 120 MHz: 7.9 W (6x86LV) 133 MHz: 8.4 W (6x86LV) 150 MHz: 9.4 W (6x86LV) |
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| Maximum Power |
80 MHz: 15.5 W (6x86) 100 MHz: 17.8 W (6x86) 110 MHz: 19.1 W (6x86) 120 MHz: 20.1 W (6x86) 133 MHz: 21.8 W (6x86) 150 MHz: 24.6 W (6x86) 100 MHz: 13.4 W (6x86L) 110 MHz: 14.3 W (6x86L) 120 MHz: 15.1 W (6x86L) 133 MHz: 16.0 W (6x86L) 150 MHz: 17.1 W (6x86L) 120 MHz: 11.2 W (6x86LV) 133 MHz: 12.1 W (6x86LV) 150 MHz: 13.2 W (6x86LV) |
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| Cooling | Required | ||
| Clock Frequencies | CPU Core Speed |
PR90: 80/40 (6x86) PR120: 100/50 PR133: 110/55 PR150: 120/60 PR166: 133/66 PR200: 150/75 |
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| L1 Cache Speed | 1.0x Core Speed | ||
| L2 Cache Speed | 1.0x External Bus Speed | ||
| External Bus Speed | 50, 55, 60, 66, or 75 MHz | ||
| Core/Bus Ratio | 2.0x, 3.0x | ||
| Miscellaneous | usual Motherboard | Single Processor Socket 5 or 7 | |
| usual Chipset | Intel 82430FX, 82430HX, 82430VX, 82430TX, or non-Intel | ||
| Pictures |
0.65 µm Die (200 KB JPG) 0.35 µm Die (273 KB JPG) 0.65 µm and 0.35 µm Open Packages (170 KB JPG) IBM ID=15h Top (65 KB JPG) and Bottom (104 KB JPG) IBM ID=17h Top (71 KB JPG) and Bottom (110 KB JPG) Cyrix ID=17h Top (63 KB JPG) and Bottom (102 KB JPG) IBM ID=22h Top (82 KB JPG) and Bottom (99 KB JPG) |
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| Processor Core | Generic Details | CISC, In-/Out-of-order and Pipelined Execution | |
| Specific Details | Dual Pipeline Design | ||
| Registers | 32 Bit Integer, 80 Bit FP, 32 Entry RAT | ||
| Pipeline Depth |
1 (Shared) plus 2x 4+2 In-/Out-of-order (Dual Pipeline) Stages, 4x FP plus 4x FP Store Queue |
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| Instruction Decoder | 2x IA-32/Cycle | ||
| Execution Units | 2x Integer, Non-pipelined FPU | ||
| Execution Speed | up to 2x IA-32/Cycle | ||
| Processor Buses | Address Bus Width | 32 Bit | |
| Data Bus Width | 64 Bit | ||
| Physical Memory | 2^32 Bit = 4 GB | ||
| Virtual Memory | 2^32 Bit = 4 GB | ||
| Logical Memory | (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB) | ||
| Multiprocessing | N/A | ||
| Power Management | HLT, STPCLK, SMI/Cyrix SMM, Suspend | ||
| Processor Caches | Level 0 | 256 Byte, Full, 32 Byte/Line, LRU | |
| Level 1 | Unified |
16 KB, 4-Way, 32 Byte/Line, Dual-ported, Write Allocate, LRU |
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| Level 2 | Unified | External, depends on Motherboard | |
| Processor Buffers | Read Buffer | ??? | |
| Write Buffer | ??? | ||
| Prefetch Queue | 64 Byte | ||
| Branch Prediction | Static | Yes | |
| Dynamic | 256 Entries, 4-Way, 4-State | ||
| RSB | 8 Entries | ||
| TLB | Main | 128 Entries, Direct, LRU | |
| Victim | 8 Entries, Full, LRU | ||
| DTE (PDEs) | 4 Entries, Full, LRU | ||
| Instruction Set | Regular | IA-32 | |
| Floating Point | Integrated | ||
| Multi Media | N/A | ||
| Processor Modes | Real, Protected, Virtual, Paging, SMM | ||
