AMD K5 (SSA5 and 5k86)
| General Details | Name | K5 | |
| Codename |
SSA5 (PR75, PR90, and PR100) 5k86 (PR120, PR133, and PR166) |
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| Family/Generation | 80586, 5th Generation | ||
| Vendor | AMD | ||
| Manufacturer | AMD | ||
| First Introduction |
Mar 27, 1996 (PR75 and PR90) Oct 7, 1996 (PR100, PR120, and PR133) Jan 13, 1997 (PR166) |
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| Physical Details | Package Type | 296 Pin PGA | |
| Package Size | 4.95 cm x 4.95 cm | ||
| Socket or Slot |
Socket 5 (up to PR133) Socket 7 (up to PR166) |
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| Transistors | 4,300,000 (includes 34 KB L1 Cache) | ||
| Process Technology |
3M, 0.50 µm, CMOS 4M, 0.35 µm, CMOS |
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| Die Size |
251 mm² (0.50 µm SSA5) 161 mm² (0.35 µm SSA5) 181 mm² (0.35 µm 5k86) |
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| Electrical Details | Split Voltage | N/A | |
| Core Voltage | 3.52 V | ||
| I/O Voltage | 3.52 V | ||
| Typical Power |
PR75: 9.5 W PR90: 11.4 W PR100: 12.7 W PR120: 9.5 W PR133: 10.6 W PR166: 12.3 W |
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| Maximum Power |
PR75: 11.6 W PR90: 13.9 W PR100: 15.5 W PR120: 12.4 W PR133: 13.7 W PR166: 16.0 W |
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| Cooling | Required | ||
| Clock Frequencies | CPU Core Speed |
PR75: 75/50 MHz PR90: 90/60 MHz PR100: 100/66 MHz PR120: 90/60 MHz PR133: 100/66 MHz PR166: 116.7/66 MHz |
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| L1 Cache Speed | 1.0x Core Speed | ||
| L2 Cache Speed | 1.0x External Bus Speed | ||
| External Bus Speed | 50, 60, or 66 MHz | ||
| Core/Bus Ratio | 1.5x (PR75..133), 1.75x (PR166) | ||
| Miscellaneous | usual Motherboard | Single Processor Socket 5 or 7 | |
| usual Chipset | Intel 82430FX, 82430HX, 82430VX, 82430TX, or non-Intel | ||
| Pictures |
0.50 µm Die (147 KB JPG) CPUID=0500h Top (52 KB JPG) and Bottom (110 KB JPG) CPUID=0501h Top (64 KB JPG) and Bottom (116 KB JPG) CPUID=0511h Top (70 KB JPG) and Bottom (113 KB JPG) CPUID=05x4h Top (72 KB JPG) and Bottom (112 KB JPG) |
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| Processor Core | Generic Details | RISC, Out-of-order and Speculative Execution | |
| Specific Details | 5x 2 + 1 = 11 Entry RS, 16 Entry ROB | ||
| Registers | 32 Bit Integer, 80 Bit FP, 40 Entry RAT ??? | ||
| Pipeline Depth | 3 (In-order) plus 3 (Out-of-order) Stages | ||
| Instruction Decoder | 1-4x IA-32/Cycle, 4x ROPs/Cycle | ||
| Execution Units | 2x ALU, 2x Load/Store, 1x Branch, 1x FPU | ||
| Execution Speed | up to 4x ROPs/Cycle | ||
| Processor Buses | Address Bus Width | 32 Bit | |
| Data Bus Width | 64 Bit | ||
| Physical Memory | 2^32 Bit = 4 GB | ||
| Virtual Memory | 2^32 Bit = 4 GB | ||
| Logical Memory | (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB) | ||
| Multiprocessing | N/A | ||
| Power Management | HLT, STPCLK, SMI/SMM | ||
| Processor Caches | Level 0 | N/A | |
| Level 1 | Code |
16 KB, 4-Way, 32 Byte/Line, SI, 2x Fetch Port (supports Split-line Acess), 5 Pre-decode Bits/Byte (adds 10 KB), Blocking, Dual Tags, RRR |
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| Data |
8 KB, 4-Way, 32 Byte/Line, MESI, Dual-ported, Blocking, Dual Tags, Write Allocate, 4 Banks, RRR |
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| Level 2 | Unified | External, depends on Motherboard | |
| Processor Buffers | Read Buffer |
16 Byte for Code Cache 16 Byte for Data Cache 16 Byte for BIU |
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| Write Buffer |
32 Byte 32 Byte (Snoop Write Buffer) 4x 4 Byte (Load/Store, L1 Data Cache to BIU) |
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| Prefetch Queue | 32 Byte | ||
| Branch Prediction | Static | Yes | |
| Dynamic | 1,024 Entries, 2-State | ||
| RSB | N/A | ||
| TLB | 4 KB Code | 128 Entries, 4-Way, ??? | |
| 4 KB Data | |||
| 4 MB Code | 4 Entry, Full, LRU | ||
| 4 MB Data | 2 Entry, Full, LRU | ||
| Instruction Set | Regular | IA-32 | |
| Floating Point | Integrated | ||
| Multi Media | N/A | ||
| Processor Modes | Real, Protected, Virtual, Paging, SMM, Probe Mode | ||
