Transmeta Efficeon
| General Details | Name | Efficeon | |
| Codenames | Astro | ||
| Family/Generation | Dynamic Translation | ||
| Vendor | Transmeta | ||
| Manufacturer |
TSMC (0.13 µm TM8300, TM8600, and TM8620) Fujitsu (0.09 µm TM8500, TM8800, and TM8820) |
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| First Introduction |
Oct 14, 2003 (MPF 2003) Jun 1, 2004 (900...1100 MHz TM8620) Sep 10, 2004 (1600 MHz TM8800) Oct 5, 2004 (2000 MHz TM8800 demo @ MPF 2004) |
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| Physical Details | Package Type |
783 Ball BGA (TM8x00) 592 Ball BGA (TM8x20) |
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| Package Size |
2.90 cm x 2.90 cm (TM8x00) 2.10 cm x 2.10 cm (TM8x20) |
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| Socket or Slot | Proprietary | ||
| Transistors |
85M (0.13 µm, includes 128+64 KB L1, 1 MB L2, NB/AGP/HTT/LPC) 85M (0.09 µm, includes 128+64 KB L1, 1 MB L2, NB/AGP/HTT/LPC) |
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| Process Technology |
7M, 0.13 µm, CMOS, Cu, SOI 8M, 0.09 µm, CMOS, Cu |
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| Die Size |
119 mm² (0.13 µm) 68 mm² (0.09 µm) |
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| Electrical Details | Split Voltage | ??? | |
| Core Voltage | ??? | ||
| L2 Voltage | ??? | ||
| I/O Voltage |
2.5 V DDR SDRAM 1.2 V HTT |
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| Typical Power | ??? | ||
| Maximum Power |
~5 W (1.0 GHz 0.13 µm) ~7 W (1.1 GHz 0.13 µm) ~12 W (1.2 GHz 0.13 µm) ~13 W (1.3 GHz 0.13 µm) |
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| Cooling | Not Required or Passive | ||
| Clock Frequencies | CPU Core Speed | 1.0...1.6 GHz | |
| L1 Cache Speed | 1.0x Core Speed | ||
| L2 Cache Speed | 1.0x Core Speed | ||
| External Bus Speed |
200 MHz DDR SDRAM 200 or 400 MHz HTT 1x, 2x, or 4x AGP 2.0 with GART ??? MHz LPC 1.0 |
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| Miscellaneous | usual Motherboard | Single Processor Mobile Platform | |
| usual Chipset | Integrated North Bridge (DDR, AGP, HTT, and LPC Controller) | ||
| Pictures |
TM8600 Top (36 KB JPG) and Bottom (39 KB JPG) 0.13 µm Die (119 KB JPG) 0.09 µm Die (75 KB JPG) TM8600 Top (37 KB JPG) TM8620 Top (31 KB JPG) |
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| Processor Core | Generic Details | VLIW, In-order Execution, 4-Gear Dynamic Translation | |
| Specific Details |
256 Bit VLIW Molecules Commit/Rollback Architecture Code Morphing Software (CMS) |
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| Registers |
32 Bit Integer, 80 Bit FP, 64 Bit MM, 128 Bit SSE and SSE2 64x/48x (Primary/Shadowed) 32 Bit General Purpose Registers 64x/48x (Primary/Shadowed) 80 Bit FP General Registers 4x/4x (Primary/Shadowed) Predicate Registers |
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| Pipeline Depth | 6 (Integer), 8 (FP), 6 (Load/Store) | ||
| Instruction Decoder |
Code morphing Software (CMS) Interprets and/or Translates x86 Code into VLIW Code |
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| Execution Units |
2x ALU 2x Load/Store/Add 2x Execute 2x FP/MM/SSE/SSE2 1x Branch 1x Alias 1x Control |
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| Execution Speed |
1x VLIW Molecule/Cycle up to 8x Atoms/Molecule |
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| Processor Buses | DDR SDRAM Bus Width | 64+8 Bit | |
| Data Bus Width | 1x 8 Bit | ||
| L2 Cache Bus Width | ???+??? Bit | ||
| Physical Memory | 2^32 Bit = 4 GB | ||
| Virtual Memory | 2^32 Bit = 4 GB | ||
| Logical Memory | (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB) | ||
| Multiprocessing | N/A | ||
| Power Management |
HLT, STPCLK, SMI/SMM, Quick Start, Deep Sleep LongRun Technology (voltage and frequency control) LongRun2 Technology (threshold voltage control, 0.09 µm) |
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| Processor Caches | Level 0 | N/A | |
| Level 1 | Code | 128 KB, 4-Way, 64 Bytes/Line | |
| Data | 64 KB, 8-Way, 32 Bytes/Line | ||
| Level 2 | TM8300/TM8500 | 0.5 MB, 4-Way, 128 Bytes/Line, ECC | |
| TM86x0/TM88x0 | 1.0 MB, 4-Way, 128 Bytes/Line, ECC | ||
| Level 3 | Translation Cache | 16...32 MB | |
| Processor Buffers | Buffers |
Alias Hardware Gated Store Buffer 48x Atom Queue in Front End 14x Write Queue and Store Buffer 32x Victim Cache (32 Bytes/Line) 4x 32 Byte WC Buffer |
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| Prefetch Queue | N/A | ||
| Branch Prediction | Yes | ||
| TLB | 256 Entries, 4-Way | ||
| Instruction Set | Regular | IA-32 | |
| Floating Point | Integrated | ||
| Multi Media | MMX, SSE, SSE2 | ||
| Processor Modes | Real, Protected, Virtual, Paging, SMM | ||
