Centaur WinChip
| General Details | Name | WinChip | |
| Codename | C6 | ||
| Family/Generation | 80586, 4th Generation, MMX | ||
| Vendor | Centaur | ||
| Manufacturer | IDT | ||
| First Introduction |
Oct 13, 1997 (180 and 200 MHz) Apr 21, 1998 (225 and 240 MHz) |
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| Physical Details | Package Type | 296 Pin PGA | |
| Package Size | 4.95 cm x 4.95 cm (PGA) | ||
| Socket or Slot | Socket 7 | ||
| Transistors | 5,400,000 (includes 2x 32 KB L1 Cache) | ||
| Process Technology | 4M, 0.35 µm, CMOS | ||
| Die Size | 88 mm² | ||
| Electrical Details | Split Voltage | N/A | |
| Core Voltage |
3.3 V (STD) 3.52 V (VRE) |
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| I/O Voltage |
3.3 V (STD) 3.52 V (VRE) |
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| Typical Power |
180 MHz: ~ 5 W (3.3 V) 180 MHz: ~ 6 W (3.52 V) 200 MHz: ~ 6 W (3.3 V) 200 MHz: ~ 7 W (3.52 V) 225 MHz: ~ 7 W (3.3 V) 225 MHz: ~ 8 W (3.52 V) 240 MHz: ~ 8 W (3.3 V) 240 MHz: ~ 9 W (3.52 V) |
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| Maximum Power |
180 MHz: 8.1 W (3.3 V) 180 MHz: 9.4 W (3.52 V) 200 MHz: 8.9 W (3.3 V) 200 MHz: 10.4 W (3.52 V) 225 MHz: 10.6 W (3.3 V) 225 MHz: 12.3 W (3.52 V) 240 MHz: 11.3 W (3.3 V) 240 MHz: 13.1 W (3.52 V) |
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| Cooling | Required | ||
| Clock Frequencies | CPU Core Speed | 180, 200, 225, 240 MHz | |
| L1 Cache Speed | 1.0x Core Speed | ||
| L2 Cache Speed | 1.0x External Bus Speed | ||
| External Bus Speed | 60, 66, or 75 MHz | ||
| Core/Bus Ratio | 3.0x, 4.0x | ||
| Miscellaneous | usual Motherboard | Single Processor Socket 7 | |
| usual Chipset | Intel 82430FX, 82430HX, 82430VX, 82430TX, or non-Intel | ||
| Pictures |
0.35 µm Die (90 KB JPG) CPUID=0540h Top (66 KB JPG) and Bottom (106 KB JPG) CPUID=0541h Top (68 KB JPG) and Bottom (107 KB JPG) | ||
| Processor Core | Generic Details | CISC, In-order Execution | |
| Specific Details | Single Pipeline Design | ||
| Registers | 32 Bit Integer, 80 Bit FP, 64 Bit MM | ||
| Pipeline Depth | 4 Stages | ||
| Instruction Decoder | 1x IA-32/Cycle | ||
| Execution Units | Integer, MMX, Non-pipelined FPU | ||
| Execution Speed | up to 1x IA-32/Cycle | ||
| Processor Buses | Address Bus Width | 32 Bit | |
| Data Bus Width | 64 Bit | ||
| Physical Memory | 2^32 Bit = 4 GB | ||
| Virtual Memory | 2^32 Bit = 4 GB | ||
| Logical Memory | (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB) | ||
| Multiprocessing | N/A | ||
| Power Management | HLT, STPCLK, SMI/SMM | ||
| Processor Caches | Level 0 | N/A | |
| Level 1 | Code | 32 KB, 2-Way, 32 Byte/Line, LRU | |
| Data | 32 KB, 2-Way, 32 Byte/Line, LRU | ||
| Level 2 | Unified | External, depends on Motherboard | |
| Processor Buffers | Read Buffer | 16 Byte | |
| Write Buffer | 4x 8 Byte | ||
| Prefetch Queue | 3 Entry Translation-to-Execution Stage Queue | ||
| Branch Prediction | Static | Yes | |
| Dynamic | N/A | ||
| RSB | 8 Entries | ||
| TLB | Code | 64 Entries, 4-Way, pseudo-LRU | |
| Data | 64 Entries, 4-Way, pseudo-LRU | ||
| PDC (PDEs) | 8 Entries, ???, LRU | ||
| Instruction Set | Regular | IA-32 | |
| Floating Point | Integrated | ||
| Multi Media | MMX | ||
| Processor Modes | Real, Protected, Virtual, Paging, SMM | ||
