Centaur WinChip 2
| General Details | Name |
WinChip2 WinChip2A, WinChip2B WinChip3 |
|
| Codename |
C6+, W2 W2A, W2B W3 |
||
| Family/Generation | 80586, 5th Generation, MMX | ||
| Vendor | Centaur | ||
| Manufacturer | IDT | ||
| First Introduction |
May 19, 1998 (samples) Sep ???, 1998 (WinChip2 200, 225 and 240 MHz) Mar ???, 1999 (WinChip2A PR200, PR233, PR266) |
||
| Physical Details | Package Type |
296 Pin PGA 296 Pin PPGA (WinChip2B) |
|
| Package Size |
4.95 cm x 4.95 cm (PGA) 4.95 cm x 4.95 cm (PPGA) |
||
| Socket or Slot | Socket 7 | ||
| Transistors |
5,900,000 (includes 2x 32 KB L1 Cache) ??? (includes 2x 64 KB L1 Cache, WinChip3) |
||
| Process Technology |
5M, 0.35 µm, CMOS 5M, 0.25 µm, CMOS |
||
| Die Size |
95 mm² (0.35 µm) 58 mm² (0.25 µm) 75 mm² (0.25 µm, WinChip3) |
||
| Electrical Details | Split Voltage |
WinChip2, WinChip2A: No WinChip2B, WinChip3: Yes (determined via Motherboard) |
|
| Core Voltage |
3.3 V (STD) 3.52 V (VRE) 2.8 V (WinChip2B, WinChip3) |
||
| I/O Voltage |
3.3 V (STD) 3.52 V (VRE) 3.3 V (WinChip2B, WinChip3) |
||
| Typical Power |
200 MHz: ~ 6 W (WinChip2 @ 3.3 V) 200 MHz: ~ 8 W (WinChip2 @ 3.52 V) 225 MHz: ~ 7 W (WinChip2 @ 3.3 V) 225 MHz: ~ 9 W (WinChip2 @ 3.52 V) 240 MHz: ~ 7 W (WinChip2 @ 3.3 V) 240 MHz: ~ 9 W (WinChip2 @ 3.52 V) 200/66 MHz: ~ 6 W (WinChip2A @ 3.3 V) 200/66 MHz: ~ 8 W (WinChip2A @ 3.52 V) 233/66 MHz: ~ 7 W (WinChip2A @ 3.3 V) 233/66 MHz: ~ 9 W (WinChip2A @ 3.52 V) 233/100 MHz: ~ 7 W (WinChip2A @ 3.3 V) 233/100 MHz: ~ 9 W (WinChip2A @ 3.52 V) 250/100 MHz: ~ 8 W (WinChip2A @ 3.3 V) 250/100 MHz: ~ 11 W (WinChip2A @ 3.52 V) |
||
| Maximum Power |
200 MHz: 8.8 W (WinChip2 @ 3.3 V) 200 MHz: 12.0 W (WinChip2 @ 3.52 V) 225 MHz: 10.0 W (WinChip2 @ 3.3 V) 225 MHz: 13.0 W (WinChip2 @ 3.52 V) 240 MHz: 10.5 W (WinChip2 @ 3.3 V) 240 MHz: 14.0 W (WinChip2 @ 3.52 V) 200/66 MHz: 8.8 W (WinChip2A @ 3.3 V) 200/66 MHz: 12.0 W (WinChip2A @ 3.52 V) 233/66 MHz: 10.0 W (WinChip2A @ 3.3 V) 233/66 MHz: 13.0 W (WinChip2A @ 3.52 V) 233/100 MHz: 10.5 W (WinChip2A @ 3.3 V) 233/100 MHz: 14.0 W (WinChip2A @ 3.52 V) 250/100 MHz: 11.8 W (WinChip2A @ 3.3 V) 250/100 MHz: 16.0 W (WinChip2A @ 3.52 V) |
||
| Cooling | Required | ||
| Clock Frequencies | CPU Core Speed |
200, 225, 240 MHz (WinChip2) PR200: 200/66 MHz (WinChip2A) PR233: 233/66 MHz (WinChip2A) PR300: 250/100 MHz (WinChip2A) PR200: 200/66 MHz (WinChip2B) PR233: 200/66 MHz (WinChip3) |
|
| L1 Cache Speed | 1.0x Core Speed | ||
| L2 Cache Speed | 1.0x External Bus Speed | ||
| External Bus Speed |
60, 66, or 75 MHz (WinChip2) 66 or 100 MHz (WinChip2A) 66 MHz (WinChip2B) 66 MHz (WinChip3) |
||
| Core/Bus Ratio |
3.0x, 4.0x (WinChip2) 2.33x, 3.0x, 3.5x (WinChip2A) 3.00x (WinChip2B) 3.00x (WinChip3) |
||
| Miscellaneous | usual Motherboard | Single Processor Socket 7 | |
| usual Chipset | Intel 82430FX, 82430HX, 82430VX, 82430TX, or non-Intel | ||
| Pictures |
0.35 µm Die (143 KB JPG) 0.25 µm Die (160 KB JPG) CPUID=0585h Top (65 KB JPG) and Bottom (120 KB JPG) CPUID=0587h Top (58 KB JPG) and Bottom (98 KB JPG) CPUID=058Ah Top (117 KB JPG) and Bottom (93 KB JPG) CPUID=0595h Top (74 KB JPG) and Bottom (93 KB JPG) | ||
| Processor Core | Generic Details | CISC, In-order Execution | |
| Specific Details | Single Pipeline Design | ||
| Registers | 32 Bit Integer, 80 Bit FP, 64 Bit MM | ||
| Pipeline Depth | 4 Stages | ||
| Instruction Decoder | 1x IA-32/Cycle, up to 2x MMX or 3DNow!/Cycle, up to 4 µOPs/Cycle | ||
| Execution Units |
Integer, Pipelined FPU, Pipelined Multiply-Add MMX, Non-pipelined Shift-Pack MMX, Pipelined Dual-Add 3DNow!, Pipelined Dual-Multiply 3DNow! |
||
| Execution Speed | 1x IA-32/Cycle, up to 2x MMX or 3DNow!/Cycle | ||
| Processor Buses | Address Bus Width | 32 Bit | |
| Data Bus Width | 64 Bit | ||
| Physical Memory | 2^32 Bit = 4 GB | ||
| Virtual Memory | 2^32 Bit = 4 GB | ||
| Logical Memory | (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB) | ||
| Multiprocessing | N/A | ||
| Power Management | HLT, STPCLK, SMI/SMM | ||
| Processor Caches | Level 0 | N/A | |
| Level 1 | Code | 32 KB, 2-Way, 32 Byte/Line, LRU | |
| Code (WinChip3) | 64 KB, 2-Way, 32 Byte/Line, LRU | ||
| Data | 32 KB, 4-Way, 32 Byte/Line, 3 Bit pseudo-LRU | ||
| Data (WinChip3) | 64 KB, 4-Way, 32 Byte/Line, ??? | ||
| Level 2 | Unified | External, depends on Motherboard | |
| Processor Buffers | Read Buffer | 16 Byte | |
| Write Buffer | 4x 8 Byte | ||
| Prefetch Queue | 3 Entry Translation-to-Execution Stage Queue | ||
| Branch Prediction | Static | Yes | |
| Dynamic | 4,096 Entries, 1-Level | ||
| RSB | 8 Entries | ||
| TLB | Code | 128 Entries, 8-Way, 7 Bit pseudo-LRU | |
| Data | 128 Entries, 8-Way, 7 Bit pseudo-LRU | ||
| PDC (PDEs) | 8 Entries, ???, LRU | ||
| Instruction Set | Regular | IA-32 | |
| Floating Point | Integrated | ||
| Multi Media | MMX, 3DNow! | ||
| Processor Modes | Real, Protected, Virtual, Paging, SMM | ||
