IA-32 architecture opcode encoding short description A direct address; no mod R/M byte; address of operand is encoded in instruction; no base register, index register, or scaling factor can be applied C reg field of mod R/M byte selects a control register D reg field of mod R/M byte selects a debug register E mod R/M byte follows opcode and specifies operand; operand is either a general register or a memory address; if it is a memory address, the address is computed from a segment register and any of the following values: a base register, an index register, a scaling factor, a displacement F flags register G reg field of mod R/M byte selects a general register I immediate data; value of operand is encoded in subsequent bytes of instruction J instruction contains a relative offset to be added to the instruction pointer register M mod R/M byte may refer only to memory O direct offset; no mod R/M byte; offset of operand is encoded in instruction; no base register, index register, or scaling factor can be applied P reg field of mod R/M byte selects a MMX register PR / N r/m field of mod R/M byte selects a MMX register; mod field of mod R/M byte must be 11b Q mod R/M byte follows opcode and specifies operand; operand is either an MMX register or a memory address; if it is a memory address, the address is computed from a segment register and any of the following values: a base register, an index register, a scaling factor, a displacement R r/m field of mod R/M byte selects a general register; mod field of mod R/M byte should be 11b S reg field of mod R/M byte selects a segment register T reg field of mod R/M byte selects a test register VD dst field of DREX byte selects a XMM register V reg field of mod R/M byte selects a XMM register VR / U r/m field of mod R/M byte selects a XMM register; mod field of mod R/M byte must be 11b W mod R/M byte follows opcode and specifies operand; operand is either a XMM register or a memory address; if it is a memory address, the address is computed from a segment register and any of the following values: a base register, an index register, a scaling factor, a displacement X memory addressed by DS:SI register pair; eg. MOVS, CMPS, OUTS, LODS Y memory addressed by ES:DI register pair; eg. MOVS, CMPS, INS, STOS, SCAS short description b byte (regardless of operand size attribute) w word (regardless of operand size attribute) d dword (regardless of operand size attribute) q qword (regardless of operand size attribute) o oword (regardless of operand size attribute) v word or dword or qword, depending on operand size attribute z word or dword or dword, depending on operand size attribute a two word or two doubleword operands in memory, depending on operand size attribute (used only by BOUND) p 32-bit or 48-bit pointer, depending on operand size attribute s six-byte pseudo-descriptor t ten-byte pseudo-descriptor general instruction format (gray areas indicate optional parts) #1 instruction prefix(es) opcode byte(s) mod R/M byte 16bit 32bit SIB byte displacement immediate #2, #3 P1 P2 P3 P4 O2 O1 D1 D2 D3 D4 I1 I2 I3 I4 SEG, REP, LOCK, 66h, 67h 0Fh xxh byte/word/dword byte/word/dword instruction prefix(es) opcode bytes mod R/M byte 16bit 32bit SIB byte displacement imm   P1 P2 P3 P4 O2 O1 O3 D1 D2 D3 D4 I1 SEG, REP, LOCK, 66h, 67h 0Fh 38h xxh byte/word/dword   3Ah byte 7Ah xxh   7Bh byte instruction prefix(es) #4 opcode bytes mod R/M byte 16bit 32bit SIB byte DREX byte displacement imm   P1 P2 P3 P4 O2 O1 O3 D1 D2 D3 D4 I1 SEG, REP, LOCK, 66h, 67h 0Fh 24h xxh byte/word/dword   25h byte notes description #1 The 15 byte instruction length limit (#GP exception) can only be exceeded by using non-redundant prefixes. #2 Most 3DNow! instructions use the immediate byte as a third opcode byte. #3 Some SSE/SSE2 instructions use the immediate byte as a condition code. #4 The use of a REX prefix will result in a #UD exception. The DREX byte is used instead.