IA-32 architecture CPUID Before trying to rely upon CPUID, a program must properly detect and sometimes enable the instruction. In particular, the program must detect the presence of a 32bit IA-32 processor, which supports the EFLAGS register. Next, if it is a Cyrix or a NexGen processor, the CPUID instruction may have to be enabled. Then the program must try to toggle the ID bit in the EFLAGS register, to determine whether the instruction is supported or not. Note that the program may face one of the early Intel P5 processors: they do neither return a vendor ID string nor the maximum supported standard level, when level 0000_0000h is queried. Finally, notice that some chips support a partially programmable CPUID instruction -- thanks to those idiot programmers who hard-coded "GenuineIntel" all over the place...   standard level 0000_0000h   input EAX=0000_0000h get maximum supported standard level and vendor ID string output EAX=xxxx_xxxxh maximum supported standard level #1 EBX-EDX-ECX vendor ID string #2 GenuineIntel Intel processor UMC UMC UMC  UMC processor AuthenticAMD AMD processor CyrixInstead Cyrix processor NexGenDriven NexGen processor CentaurHauls Centaur processor RiseRiseRise Rise Technology processor SiS SiS SiS  SiS processor GenuineTMx86 Transmeta processor Geode by NSC National Semiconductor processor notes description #1 According to [1] and [2] the pre-B0 step Intel P5 processors return EAX=0000_05xxh. #2 According to [1] and [2] the pre-B0 step Intel P5 processors don't return a vendor ID string.   standard level 0000_0001h   input EAX=0000_0001h get processor type/family/model/stepping and feature flags output EAX=xxxx_xxxxh processor type/family/model/stepping extended family (add) The extended processor family is encoded in bits 27...20. 00+F Intel P4 AMD K8 Transmeta Efficeon 01+F AMD K8L Intel Itanium 2 (IA-64) 02+0 Intel Itanium 2 DC (IA-64) extended model (concat) The extended processor model is encoded in bits 19...16. AMD K8 0 130 nm Rev C 1 90 nm Rev D 2 90 nm Rev E 4 90 nm Rev F 5 90 nm Rev F 6 65 nm Rev G 7 65 nm Rev G Intel Core 2 1 65 nm SC with 1 MB on-die L2 1 45 nm DC with 6 MB on-die L2 type The processor type is encoded in bit 13 and bit 12. 11b reserved 10b secondary processor (for MP) 01b Overdrive processor 00b primary processor family The family is encoded in bits 11...8. 4 most 80486s AMD 5x86 Cyrix 5x86 5 Intel P5, P54C, P55C, P24T NexGen Nx586 Cyrix M1 Cyrix MediaGX Geode AMD K5, K6 Centaur C6, C2, C3 Rise mP6 SiS 55x Transmeta Crusoe 6 Intel P6, P2, P3, PM, Core 2 AMD K7 Cyrix M2 VIA C3 7 Intel Itanium (IA-64) F refer to extended family 0 refer to extended family model The model is encoded in bits 7...4. Intel 80486 0 i80486DX-25/33 1 i80486DX-50 2 i80486SX 3 i80486DX2 4 i80486SL 5 i80486SX2 7 i80486DX2WB 8 i80486DX4 9 i80486DX4WB UMC 80486 1 U5D 2 U5S AMD 80486 3 80486DX2 7 80486DX2WB 8 80486DX4 9 80486DX4WB A Elan SC400 E 5x86 F 5x86WB Cyrix 5x86 9 5x86 Cyrix MediaGX 4 GX, GXm Intel P5-core 0 P5 A-step 1 P5 2 P54C 3 P24T Overdrive 4 P55C 7 P54C 8 P55C (0.25µm) NexGen Nx586 0 Nx586 or Nx586FPU (only later ones) Cyrix M1 2 6x86 Cyrix M2 0 6x86MX Geode 4 GX1, GXLV, GXm 5 GX2 A LX AMD K5 0 SSA5 (PR75, PR90, PR100) 1 5k86 (PR120, PR133) 2 5k86 (PR166) 3 5k86 (PR200) AMD K6 6 K6 (0.30 µm) 7 K6 (0.25 µm) 8 K6-2 9 K6-III D K6-2+ or K6-III+ (0.18 µm) Centaur 4 C6 8 C2 9 C3 VIA C3 5 Cyrix M2 core 6 WinChip C5A core 7 WinChip C5B core (if stepping = 0...7) 7 WinChip C5C core (if stepping = 8...F) 8 WinChip C5N core (if stepping = 0...7) 9 WinChip C5XL core (if stepping = 0...7) 9 WinChip C5P core (if stepping = 8...F) 10 WinChip C5J core Rise 0 mP6 (0.25 µm) 2 mP6 (0.18 µm) SiS 0 55x Transmeta Crusoe 4 TM3x00 and TM5x00 Intel P6-core 0 P6 A-step 1 P6 3 P2 (0.28 µm) 5 P2 (0.25 µm) 6 P2 with on-die L2 cache 7 P3 (0.25 µm) 8 P3 (0.18 µm) with 256 KB on-die L2 A P3 (0.18 µm) with 2 MB on-die L2 B P3 (0.13 µm) with 512 KB on-die L2 9 PM (0.13 µm) with 1 MB on-die L2 D PM (0.09 µm) with 2 MB on-die L2 E PM DC (65 nm) with 2 MB on-die L2 F Core 2 DC (65 nm) with 4 MB on-die L2 16 Core 2 SC (65 nm) with 1 MB on-die L2 17 Core 2 DC (45 nm) with 6 MB on-die L2 1C Atom (45 nm) with 512 KB on-die L2 AMD K7 1 Athlon (0.25 µm) 2 Athlon (0.18 µm) 3 Duron (SF core) 4 Athlon (TB core) 6 Athlon (PM core) 7 Duron (MG core) 8 Athlon (TH/AP core) A Athlon (BT core) AMD K8 xx00b Socket 754 or Socket S1 xx01b Socket 940 or Socket F1207 xx10b if Rev CG, then see K8 erratum #108 xx11b Socket 939 or Socket AM2 01xxb SH (SC 1024 KB) 11xxb DH (SC 512 KB) 10xxb CH (SC 256 KB) 00xxb JH (DC 1024 KB) 10xxb BH (DC 512 KB) AMD K8L 0 Rev A (0=A0, 1=A1, 2=A2) 2 Rev B (0=B0, 1=B1, A=BA, 2=B2, 3=B3) Intel P4-core 0 P4 (0.18 µm) 1 P4 (0.18 µm) 2 P4 (0.13 µm) 3 P4 (0.09 µm) 4 P4 (0.09 µm) 6 P4 (65 nm) Transmeta Efficeon 2 TM8000 (130 nm) 2 TM8000 (90 nm CMS 6.0) 3 TM8000 (90 nm CMS 6.1+) Intel Itanium 0 Merced (0.18 µm) Intel Itanium 2 0 McKinley (0.18 µm) 1 Madison or Deerfield (0.13 µm) 2 Madison 9M (0.13 µm) Intel Itanium 2 DC 0 Montecito (0.09 µm) stepping The stepping is encoded in bits 3...0. The stepping values are processor-specific. EBX=aall_ccbbh brand ID The brand ID is encoded in bits 7...0. 00h not supported 01h 0.18 µm Intel Celeron 02h 0.18 µm Intel Pentium III 03h 0.18 µm Intel Pentium III Xeon 03h 0.13 µm Intel Celeron 04h 0.13 µm Intel Pentium III 07h 0.13 µm Intel Celeron mobile 06h 0.13 µm Intel Pentium III mobile 0Ah 0.18 µm Intel Celeron 4 08h 0.18 µm Intel Pentium 4 09h 0.13 µm Intel Pentium 4 0Eh 0.18 µm Intel Pentium 4 Xeon 0Bh 0.18 µm Intel Pentium 4 Xeon MP 0Bh 0.13 µm Intel Pentium 4 Xeon 0Ch 0.13 µm Intel Pentium 4 Xeon MP 08h 0.13 µm Intel Celeron 4 mobile (0F24h) 0Fh 0.13 µm Intel Celeron 4 mobile (0F27h) 0Eh 0.13 µm Intel Pentium 4 mobile (production) 0Fh 0.13 µm Intel Pentium 4 mobile (samples) 11h mobile Intel ??? processor 12h 0.13 µm Intel Celeron M 12h 0.09 µm Intel Celeron M 13h mobile Intel Celeron ? processor 14h Intel Celeron ? processor 15h mobile Intel ??? processor 16h 0.13 µm Intel Pentium M 16h 0.09 µm Intel Pentium M 17h mobile Intel Celeron ? processr AMD see extended level 8000_0001h with ID=0000_0765_0000_0000b and NN=4_3210b CLFLUSH The CLFLUSH (8-byte) chunk count is encoded in bits 15...8. CPU count The logical processor count is encoded in bits 23...16. APIC ID The (fixed) default APIC ID is encoded in bits 31...24. ECX=xxxx_xxxxh feature flags description bits 31...29 reserved bit 28 (AVX) AVX bit 27 (OSXSAVE) non-privileged read-only copy of current CR4.OSXSAVE value bit 26 (XSAVE) CR4.OSXSAVE, XCRn, XGETBV, XSETBV, XSAVE, XRSTOR also see standard level 0000_000Dh bit 25 (AES) AES* bit 24 reserved bit 23 (POPCNT) POPCNT bit 22 (MOVBE) MOVBE bit 21 (x2APIC) x2APIC, APIC_BASE.EXTD, MSRs 0000_0800h...0000_0BFFh 64-bit ICR (+030h but not +031h), no DFR (+00Eh), SELF_IPI (+040h) also see standard level 0000_000Bh bit 20 (SSE4.2) SSE4.2 bit 19 (SSE4.1) SSE4.1, MXCSR, CR4.OSXMMEXCPT, #XF bit 18 (DCA) Direct Cache Access (that is, the ability to prefetch data from MMIO) also see standard level 0000_0009h bit 17 reserved bit 16 reserved bit 15 (PDCM) Performance Debug Capability MSR bit 14 (ETPRD) MISC_ENABLE.ETPRD bit 13 (CX16) CMPXCHG16B bit 12 (FMA) FMA bit 11 reserved bit 10 (CID) context ID: the L1 data cache can be set to adaptive or shared mode MISC_ENABLE.L1DCCM bit 9 (SSSE3) SSSE3 bit 8 (TM2) MISC_ENABLE.TM2E THERM_INTERRUPT and THERM_STATUS MSRs xAPIC thermal LVT entry THERM2_CONTROL MSR bit 7 (EST) Enhanced SpeedStep Technology bit 6 (SMX) CR4.SMXE, GETSEC bit 5 (VMX) CR4.VMXE, VM* and VM* bit 4 (DSCPL) CPL-qualified Debug Store bit 3 (MON) MONITOR/MWAIT, MISC_ENABLE.MONE, MISC_ENABLE.LCMV MONITOR_FILTER_LINE_SIZE MSR also see standard level 0000_0005h setting MISC_ENABLE.MONE=0 causes MON=0 bit 2 (DTES64) 64-bit Debug Trace and EMON Store MSRs bit 1 (PCLMUL) PCLMULQDQ bit 0 (SSE3) SSE3, MXCSR, CR4.OSXMMEXCPT, #XF, if FPU=1 then also FISTTP EDX=xxxx_xxxxh feature flags description bit 31 (PBE) Pending Break Event, STPCLK, FERR#, MISC_ENABLE.PBE bit 30 (IA-64) IA-64, JMPE Jv, JMPE Ev bit 29 (TM1) MISC_ENABLE.TM1E THERM_INTERRUPT and THERM_STATUS MSRs xAPIC thermal LVT entry bit 28 (HTT) Hyper-Threading Technology, PAUSE bit 27 (SS) selfsnoop bit 26 (SSE2) SSE2, MXCSR, CR4.OSXMMEXCPT, #XF bit 25 (SSE) SSE, MXCSR, CR4.OSXMMEXCPT, #XF bit 24 (FXSR) FXSAVE/FXRSTOR, CR4.OSFXSR bit 23 (MMX) MMX bit 22 (ACPI) THERM_CONTROL MSR bit 21 (DTES) Debug Trace and EMON Store MSRs bit 20 reserved bit 19 (CLFL) CLFLUSH bit 18 (PSN) PSN (see standard level 0000_0003h), MISC_CTL.PSND #1 bit 17 (PSE36) 4 MB PDE bits 16...13, CR4.PSE bit 16 (PAT) PAT MSR, PDE/PTE.PAT bit 15 (CMOV) CMOVcc, if FPU=1 then also FCMOVcc/F(U)COMI(P) bit 14 (MCA) MCG_*/MCn_* MSRs, CR4.MCE, #MC bit 13 (PGE) PDE/PTE.G, CR4.PGE bit 12 (MTRR) MTRR* MSRs bit 11 (SEP) SYSENTER/SYSEXIT, SEP_* MSRs #2 bit 10 reserved bit 9 (APIC) APIC #3, #4 bit 8 (CX8) CMPXCHG8B #5 bit 7 (MCE) MCAR/MCTR MSRs, CR4.MCE, #MC bit 6 (PAE) 64bit PDPTE/PDE/PTEs, CR4.PAE bit 5 (MSR) MSRs, RDMSR/WRMSR bit 4 (TSC) TSC, RDTSC, CR4.TSD (doesn't imply MSR=1) bit 3 (PSE) PDE.PS, PDE/PTE.res, CR4.PSE, #PF(1xxxb) bit 2 (DE) CR4.DE, DR7.RW=10b, #UD on MOV from/to DR4/5 bit 1 (VME) CR4.VME/PVI, EFLAGS.VIP/VIF, TSS32.IRB bit 0 (FPU) FPU notes description #1 If the PSN has been disabled, then the PSN feature flag will read as 0. In addition the value for the maximum supported standard level (reported by standard level 0000_0000h, register EAX) will be lower. #2 The Intel P6 processor does not support SEP, but inadvertently reports it. #3 If the APIC has been disabled, then the APIC feature flag will read as 0. #4 Early AMD K5 processors (SSA5) inadvertently used this bit to report PGE support. #5 Some processors do support CMPXCHG8B, but don't report it by default. This is due to a Windows NT bug.   standard level 0000_0002h   input EAX=0000_0002h get processor configuration descriptors output AL number of times this level must be queried to obtain all configuration descriptors #1 EAX.15...8 EAX.23...16 EAX.31...24 EBX.0...7 EBX.15...8 EBX.23...16 EBX.31...24 ECX.0...7 ECX.15...8 ECX.23...16 ECX.31...24 EDX.0...7 EDX.15...8 EDX.23...16 EDX.31...24 configuration descriptors #2 value description 00h null descriptor (=unused descriptor) 01h code TLB, 4K pages, 4 ways, 32 entries 02h code TLB, 4M pages, fully, 2 entries 03h data TLB, 4K pages, 4 ways, 64 entries 04h data TLB, 4M pages, 4 ways, 8 entries 05h data TLB, 4M pages, 4 ways, 32 entries 06h code L1 cache, 8 KB, 4 ways, 32 byte lines 08h code L1 cache, 16 KB, 4 ways, 32 byte lines 0Ah data L1 cache, 8 KB, 2 ways, 32 byte lines 0Bh code TLB, 4M pages, 4 ways, 4 entries 0Ch data L1 cache, 16 KB, 4 ways, 32 byte lines 0Eh data L1 cache, 24 KB, 6 ways, 64 byte lines 10h data L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64) 15h code L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64) 1Ah code and data L2 cache, 96 KB, 6 ways, 64 byte lines (IA-64) 22h code and data L3 cache, 512 KB, 4 ways (!), 64 byte lines, dual-sectored 23h code and data L3 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored 25h code and data L3 cache, 2048 KB, 8 ways, 64 byte lines, dual-sectored 29h code and data L3 cache, 4096 KB, 8 ways, 64 byte lines, dual-sectored 2Ch data L1 cache, 32 KB, 8 ways, 64 byte lines 30h code L1 cache, 32 KB, 8 ways, 64 byte lines 39h code and data L2 cache, 128 KB, 4 ways, 64 byte lines, sectored 3Ah code and data L2 cache, 192 KB, 6 ways, 64 byte lines, sectored 3Bh code and data L2 cache, 128 KB, 2 ways, 64 byte lines, sectored 3Ch code and data L2 cache, 256 KB, 4 ways, 64 byte lines, sectored 3Dh code and data L2 cache, 384 KB, 6 ways, 64 byte lines, sectored 3Eh code and data L2 cache, 512 KB, 4 ways, 64 byte lines, sectored 40h no integrated L2 cache (P6 core) or L3 cache (P4 core) 41h code and data L2 cache, 128 KB, 4 ways, 32 byte lines 42h code and data L2 cache, 256 KB, 4 ways, 32 byte lines 43h code and data L2 cache, 512 KB, 4 ways, 32 byte lines 44h code and data L2 cache, 1024 KB, 4 ways, 32 byte lines 45h code and data L2 cache, 2048 KB, 4 ways, 32 byte lines 46h code and data L3 cache, 4096 KB, 4 ways, 64 byte lines 47h code and data L3 cache, 8192 KB, 8 ways, 64 byte lines 48h code and data L2 cache, 3072 KB, 12 ways, 64 byte lines 49h code and data L3 cache, 4096 KB, 16 ways, 64 byte lines (P4) or code and data L2 cache, 4096 KB, 16 ways, 64 byte lines (Core 2) 4Ah code and data L3 cache, 6144 KB, 12 ways, 64 byte lines 4Bh code and data L3 cache, 8192 KB, 16 ways, 64 byte lines 4Ch code and data L3 cache, 12288 KB, 12 ways, 64 byte lines 4Dh code and data L3 cache, 16384 KB, 16 ways, 64 byte lines 4Eh code and data L2 cache, 6144 KB, 24 ways, 64 byte lines 4Fh code TLB, 4K pages, ???, 32 entries 50h code TLB, 4K/4M/2M pages, fully, 64 entries 51h code TLB, 4K/4M/2M pages, fully, 128 entries 52h code TLB, 4K/4M/2M pages, fully, 256 entries 56h L0 data TLB, 4M pages, 4 ways, 16 entries 57h L0 data TLB, 4K pages, 4 ways, 16 entries 59h L0 data TLB, 4K pages, fully, 16 entries 5Bh data TLB, 4K/4M pages, fully, 64 entries 5Ch data TLB, 4K/4M pages, fully, 128 entries 5Dh data TLB, 4K/4M pages, fully, 256 entries 60h data L1 cache, 16 KB, 8 ways, 64 byte lines, sectored 66h data L1 cache, 8 KB, 4 ways, 64 byte lines, sectored 67h data L1 cache, 16 KB, 4 ways, 64 byte lines, sectored 68h data L1 cache, 32 KB, 4 ways, 64 byte lines, sectored 70h trace L1 cache, 12 KµOPs, 8 ways 71h trace L1 cache, 16 KµOPs, 8 ways 72h trace L1 cache, 32 KµOPs, 8 ways 73h trace L1 cache, 64 KµOPs, 8 ways 77h code L1 cache, 16 KB, 4 ways, 64 byte lines, sectored (IA-64) 78h code and data L2 cache, 1024 KB, 4 ways, 64 byte lines 79h code and data L2 cache, 128 KB, 8 ways, 64 byte lines, dual-sectored 7Ah code and data L2 cache, 256 KB, 8 ways, 64 byte lines, dual-sectored 7Bh code and data L2 cache, 512 KB, 8 ways, 64 byte lines, dual-sectored 7Ch code and data L2 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored 7Dh code and data L2 cache, 2048 KB, 8 ways, 64 byte lines 7Eh code and data L2 cache, 256 KB, 8 ways, 128 byte lines, sect. (IA-64) 7Fh code and data L2 cache, 512 KB, 2 ways, 64 byte lines 80h code and data L2 cache, 512 KB, 8 ways, 64 byte lines 81h code and data L2 cache, 128 KB, 8 ways, 32 byte lines 82h code and data L2 cache, 256 KB, 8 ways, 32 byte lines 83h code and data L2 cache, 512 KB, 8 ways, 32 byte lines 84h code and data L2 cache, 1024 KB, 8 ways, 32 byte lines 85h code and data L2 cache, 2048 KB, 8 ways, 32 byte lines 86h code and data L2 cache, 512 KB, 4 ways, 64 byte lines 87h code and data L2 cache, 1024 KB, 8 ways, 64 byte lines 88h code and data L3 cache, 2048 KB, 4 ways, 64 byte lines (IA-64) 89h code and data L3 cache, 4096 KB, 4 ways, 64 byte lines (IA-64) 8Ah code and data L3 cache, 8192 KB, 4 ways, 64 byte lines (IA-64) 8Dh code and data L3 cache, 3072 KB, 12 ways, 128 byte lines (IA-64) 90h code TLB, 4K...256M pages, fully, 64 entries (IA-64) 96h data L1 TLB, 4K...256M pages, fully, 32 entries (IA-64) 9Bh data L2 TLB, 4K...256M pages, fully, 96 entries (IA-64) B0h code TLB, 4K pages, 4 ways, 128 entries B1h code TLB, 4M pages, 4 ways, 4 entries and code TLB, 2M pages, 4 ways, 8 entries B3h data TLB, 4K pages, 4 ways, 128 entries B4h data TLB, 4K pages, 4 ways, 256 entries BAh data TLB, 4K pages, 4 ways, 64 entries C0h data TLB, 4K/4M pages, 4 ways, 8 entries F0h 64 byte prefetching F1h 128 byte prefetching value description 70h Cyrix specific: code and data TLB, 4K pages, 4 ways, 32 entries 74h Cyrix specific: ??? 77h Cyrix specific: ??? 80h Cyrix specific: code and data L1 cache, 16 KB, 4 ways, 16 byte lines 82h Cyrix specific: ??? 84h Cyrix specific: ??? value description others reserved example (here: P6) EAX=0302_0101h EBX=0000_0000h ECX=0000_0000h EDX=0604_0A43h Because AL is 01h, one invocation of the level is enough to obtain all the configuration descriptors. All of them are valid because their highest bits are 0. This P6 processor includes a 4K/M code/data TLB, an 8+8 KB code/data L1 cache and an integrated 512 KB code and data L2 cache. notes description #1 In a MP system special precautions must be taken when executing standard level 0000_0002h more than once. In particular it must be ensured that the same CPU is used during that entire process. #2 Programs must no expect any particular order for the reported configuration descriptors.   standard level 0000_0003h   input EAX=0000_0003h get processor serial number #1 output EAX=xxxx_xxxxh processor serial number (Transmeta Efficeon processors only) EBX=xxxx_xxxxh processor serial number (Transmeta Crusoe and Efficeon processors only) ECX=xxxx_xxxxh processor serial number EDX=xxxx_xxxxh processor serial number note description #1 This level is only supported and enabled if the PSN feature flag is set. The reported processor serial number should be combined with the vendor ID string and the processor type/family/model/stepping value, to distinguish cases in which two processors from different vendors happen to have the same serial number. Finally, it should be noted that most vendors can not guarantee that their serial numbers are truely unique.   standard level 0000_0004h   input EAX=0000_0004h get cache configuration descriptors #1 ECX=xxxx_xxxxh cache level to query (e.g. 0=L1D, 1=L2, or 0=L1D, 1=L1I, 2=L2) output EAX bits description 31...26 cores per package - 1 25...14 threads per cache - 1 13...10 reserved 9 fully associative? 8 self-initializing? 7...5 cache level (starts at 1) 4...0 cache type (0=null, 1=data, 2=code, 3=unified, 4...31=reserved) EBX bits description 31...22 ways of associativity - 1 21...12 physical line partitions - 1 11...0 system coherency line size - 1 ECX bits description 31...0 sets - 1 EDX bits description 31...10 reserved 1 inclusive of lower levels? 0 write-back invalidate? notes description #1 This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.   standard level 0000_0005h   input EAX=0000_0005h get MON information #1 output EAX bits description 31...16 reserved 15...0 smallest monitor line size in bytes EBX bits description 31...16 reserved 15...0 largest monitor line size in bytes ECX bits description 31...2 reserved 1 treat interrupts as break events, even when interrupts are disabled 0 enumeration of MWAIT extensions (beyond EAX and EBX) EDX bits description 31...20 reserved 19...16 number of C4 sub C-states for MWAIT 15...12 number of C3 sub C-states for MWAIT 11...8 number of C2 sub C-states for MWAIT 7...4 number of C1 sub C-states for MWAIT 3...0 number of C0 sub C-states for MWAIT notes description #1 This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.   standard level 0000_0006h   input EAX=0000_0006h get power management information #1 output EAX bits description 31...3 reserved 2 operating point protection (protect CPU's ratio/VID points) #2 1 dynamic acceleration enabled (MISC.ENABLE.DAD=0) 0 digital thermometer EBX bits description 31...4 reserved 3...0 number of programmable digital thermometer interrupt thresholds ECX bits description 31...1 reserved 0 ACNT/MCNT notes description #1 This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. #2 The implementation of OPP is processor and stepping specific. On certain Pentium 4 processors, the protection mechanism is Snap-to-VID and it is enabled if the bit is set.   standard level 0000_0009h   input EAX=0000_0009h get DCA parameters #1 output EAX bits description 31...0 value of PLATFORM_DCA_CAP MSR (0000_01F8h, bits 31...0) notes description #1 This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.   standard level 0000_000Ah   input EAX=0000_000Ah get architectural PeMo information #1 output EAX bits description 31...24 length of EBX bit vector 23...16 bit width of PeMo counter(s) 15...8 number of PeMo counters per logical processor 7...0 revision EBX bits description 31...7 reserved 6 branch mispredicts retired event unavailable 5 branch instructions retired event unavailable 4 last level cache misses event unavailable 3 last level cache references event unavailable 2 reference cycles event unavailable 1 instructions retired event unavailable 0 core cycles event unavailable EDX bits description 31...13 reserved 12...5 bit width of fixed-function PeMo counters (if revision > 1) 4...0 number of fixed-function PeMo counters (if revision > 1) notes description #1 This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.   standard level 0000_000Bh   input EAX=0000_000Bh get topology enumeration information #1 ECX=0000_00xxh level to query (00h=SMT) output EAX bits description 31...5 reserved 4...0 number of bits to shift x2APIC ID right to get unique topology ID of next level type all logical processors with same next level ID share current level EBX bits description 31...16 reserved 15...0 number of enabled logical processors at this level ECX bits description 31...16 reserved 15...8 level type (00h=invalid, 01h=SMT, 02h=core, 03h...FFh=reserved 7...0 level number (same as input) EDX bits description 31...0 x2APIC ID of current logical processor notes description #1 This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.   standard level 0000_000Dh   input EAX=0000_000Dh get extended state enumeration #1 ECX=0000_00xxh level to query (0=main, 1=reserved, 2...62=sub as per XCR0.n) output (main) EAX bits description 31...0 valid XCR0.31...0 bits EBX bits description 31...0 current size (in bytes) of XSAVE/XRSTOR area (as per current XCR0) ECX bits description 31...0 max. size (in bytes) of XSAVE/XRSTOR area (incl. XSAVE.HEADER) EDX bits description 31...0 valid XCR0.63...32 bits output (res.) EAX bits description 31...0 reserved EBX bits description 31...0 reserved ECX bits description 31...0 reserved EDX bits description 31...0 reserved output (sub) EAX bits description 31...0 size (in bytes) in XSAVE/XRSTOR area for XCR0.n (n=ECX=2...62) 0 if n was invalid EBX bits description 31...0 offset (in bytes) in XSAVE/XRSTOR area for XCR0.n (n=ECX=2...62) 0 if n was invalid ECX bits description 31...0 reserved 0 if n was invalid EDX bits description 31...0 reserved 0 if n was invalid notes description #1 This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.   extended level 8000_0000h   input EAX=8000_0000h get maximum supported extended level and vendor ID string output EAX=xxxx_xxxxh maximum supported extended level EBX-EDX-ECX vendor ID string AuthenticAMD AMD processor reserved Cyrix processor reserved Centaur processor reserved Intel processor TransmetaCPU Transmeta processor reserved National Semiconductor processor (GX1, GXLV, GXm) Geode by NSC National Semiconductor processor (GX2)   extended level 8000_0001h   input EAX=8000_0001h get processor family/model/stepping and features flags output EAX=xxxx_xxxxh processor family/model/stepping extended family (add) The extended processor family is encoded in bits 27...20. 00+F AMD K8 Transmeta Efficeon 01+F AMD K8L extended model (concat) The extended processor model is encoded in bits 19...16. AMD K8 0 130 nm Rev C 1 90 nm Rev D 2 90 nm Rev E 4 90 nm Rev F 5 90 nm Rev F 6 65 nm Rev G 7 65 nm Rev G family The family is encoded in bits 11...8. 5 AMD K5 Geode Centaur C2 and C3 Transmeta Crusoe 6 AMD K6 VIA C3 7 AMD K7 F refer to extended family model The model is encoded in bits 7...4. AMD K5 1 5k86 (PR120 or PR133) 2 5k86 (PR166) 3 5k86 (PR200) AMD K6 6 K6 (0.30 µm) 7 K6 (0.25 µm) 8 K6-2 9 K6-III D K6-2+ or K6-III+ (0.18 µm) AMD K7 1 Athlon (0.25 µm) 2 Athlon (0.18 µm) 3 Duron (SF core) 4 Athlon (TB core) 6 Athlon (PM core) 7 Duron (MG core) 8 Athlon (TH/AP core) A Athlon (BT core) AMD K8 xx00b Socket 754 or Socket S1 xx01b Socket 940 or Socket F1207 xx10b if Rev CG, then see K8 erratum #108 xx11b Socket 939 or Socket AM2 01xxb SH (SC 1024 KB) 11xxb DH (SC 512 KB) 10xxb CH (SC 256 KB) 00xxb JH (DC 1024 KB) 10xxb BH (DC 512 KB) AMD K8L 0 Rev A (0=A0, 1=A1, 2=A2) 2 Rev B (0=B0, 1=B1, A=BA, 2=B2, 3=B3) Geode 4 GX1, GXLV, GXm 5 GX2 5 LX Centaur 8 C2 9 C3 VIA C3 5 Cyrix M2 core 6 WinChip C5A core 7 WinChip C5B core (if stepping = 0...7) 7 WinChip C5C core (if stepping = 8...F) 8 WinChip C5N core (if stepping = 0...7) 9 WinChip C5XL core (if stepping = 0...7) 9 WinChip C5P core (if stepping = 8...F) 10 WinChip C5J core Transmeta Crusoe 4 TM3x00 and TM5x00 Transmeta Efficeon 2 TM8000 (130 nm) 2 TM8000 (90 nm CMS 6.0) 3 TM8000 (90 nm CMS 6.1+) stepping The stepping is encoded in bits 3...0. The stepping values are processor-specific. EBX=x000_xxxxh package type The package type is encoded in bits 31...28. AMD K8L 0000b Socket F1207 0001b Socket AM2 0011b Socket G3 other reserved brand ID The brand ID is encoded in bits 15...0. AMD K8 DDR1 ID = bits 15...6 = (value >> 6) & 3FFh NN = bits 5...0 = value & 3Fh   for NN=1...63: XX = 22 + NN for NN=1...30: YY = 38 + (2 * NN) for NN=1...63: ZZ = 24 + NN for NN=1...63: TT = 24 + NN for NN=1...11: RR = 45 + (5 * NN) for NN=1...31: EE = 9 + NN 00h engineering sample 04h AMD Athlon 64 XX00+ 05h AMD Athlon 64 X2 XX00+ 08h AMD Athlon 64 XX00+ mobile 09h AMD Athlon 64 XX00+ mobile, low power 0Ah AMD Turion 64 ML-XX 0Bh AMD Turion 64 MT-XX 0Ch AMD Opteron 1YY 0Dh AMD Opteron 1YY 0Eh AMD Opteron 1YY HE 0Fh AMD Opteron 1YY EE 10h AMD Opteron 2YY 11h AMD Opteron 2YY 12h AMD Opteron 2YY HE 13h AMD Opteron 2YY EE 14h AMD Opteron 8YY 15h AMD Opteron 8YY 16h AMD Opteron 8YY HE 17h AMD Opteron 8YY EE 18h AMD Athlon 64 EE00+ 1Dh AMD Athlon XP-M XX00+ mobile 1Eh AMD Athlon XP-M XX00+ mobile, low power 20h AMD Athlon XP XX00+ 21h AMD Sempron TT00+ mobile, 32-bit 23h AMD Sempron TT00+ mobile, 32-bit, low power 22h AMD Sempron TT00+, 32-bit 26h AMD Sempron TT00+, 64-bit 24h AMD Athlon 64 FX-ZZ 29h AMD Opteron DC 1RR SE 2Ah AMD Opteron DC 2RR SE 2Bh AMD Opteron DC 8RR SE 2Ch AMD Opteron DC 1RR 2Dh AMD Opteron DC 1RR 2Eh AMD Opteron DC 1RR HE 2Fh AMD Opteron DC 1RR EE 30h AMD Opteron DC 2RR 31h AMD Opteron DC 2RR 32h AMD Opteron DC 2RR HE 33h AMD Opteron DC 2RR EE 34h AMD Opteron DC 8RR 35h AMD Opteron DC 8RR 36h AMD Opteron DC 8RR HE 37h AMD Opteron DC 8RR EE 38h AMD Opteron DC 1RR 39h AMD Opteron DC 2RR 3Ah AMD Opteron DC 8RR other unknown AMD K8 DDR2 S = socket (see CPUID model bits 1...0) CC = core count - 1 (see NB capabilities register) ID = bits 13...9 PL = bits 8...6 and 14 NN = bits 15 and 5...0   RR = -1 + NN* PP = 26 + NN TT = 15 + (CC * 10) + NN ZZ = 57 + NN YY = 29 + NN * 000001b...000010b/100010b...111111b = 1...2/34...63 are reserved S=any CC=? ID=00h PL=0h engineering sample S=AM2 CC=0 ID=06h PL=4h AMD Sempron TT00+ S=AM2 CC=0 ID=06h PL=8h AMD Sempron TT00+ S=AM2 CC=0 ID=04h PL=4h AMD Athlon 64 TT00+ S=AM2 CC=0 ID=04h PL=8h AMD Athlon 64 TT00+ S=AM2 CC=1 ID=04h PL=2h AMD Athlon 64 X2 TT00+ S=AM2 CC=1 ID=04h PL=6h AMD Athlon 64 X2 TT00+ S=AM2 CC=1 ID=04h PL=8h AMD Athlon 64 X2 TT00+ S=AM2 CC=1 ID=05h PL=Ch AMD Athlon 64 DC FX-ZZ S=S1 CC=1 ID=02h PL=Ch AMD Turion 64 X2 TL-YY S=AM2 CC=1 ID=01h PL=Ah AMD Opteron DC 12RR S=AM2 CC=1 ID=01h PL=Ch AMD Opteron DC 12RR SE S=F1207 CC=1 ID=01h PL=6h AMD Opteron DC 22RR HE S=F1207 CC=1 ID=01h PL=Ah AMD Opteron DC 22RR S=F1207 CC=1 ID=01h PL=Ch AMD Opteron DC 22RR SE S=F1207 CC=1 ID=04h PL=6h AMD Opteron DC 82RR HE S=F1207 CC=1 ID=04h PL=Ah AMD Opteron DC 82RR S=F1207 CC=1 ID=04h PL=Ch AMD Opteron DC 82RR SE AMD K8L PT = package type (se EBX bits 31...28) NC = number of cores (see level 8000_0008h)   PG = bit 15 S1 = bits 14...11 M = bits 10...4 S2 = bits 3...0 M=0 PG=0 engineering sample M=0 PG=1 thermal testing kit PT=0 PG=0 NC=1 S1=0h AMD Opteron DC 83 PT=0 PG=0 NC=1 S1=1h AMD Opteron DC 23 PT=0 PG=0 NC=3 S1=0h AMD Opteron QC 83 PT=0 PG=0 NC=3 S1=1h AMD Opteron QC 23 PT=0 PG=0 NC=3 S1=2h embedded AMD Opteron QC 83 PT=0 PG=0 NC=3 S1=3h embedded AMD Opteron QC 23 PT=0 PG=0 NC=3 S1=4h embedded AMD Opteron QC 13 PT=0 PG=0 NC=x S2=Ah  SE PT=0 PG=0 NC=x S2=Bh  HE PT=0 PG=0 NC=x S2=Ch  EE PT=0 PG=0 NC=x S2=Fh (empty) PT=1 PG=0 NC=3 S1=2h AMD Phenom PT=1 PG=0 NC=3 S2=0h 00 QC PT=1 PG=0 NC=3 S2=2h 00B QC PT=1 PG=0 NC=3 S2=Dh  QC PT=1 PG=0 NC=x S2=Fh (empty) ECX=xxxx_xxxxh feature flags description of indicated feature bits 31...14 reserved bit 13 (WDT) watchdog timer bit 12 (SKINIT) SKINIT, STGI, DEV bit 11 (SSE5A) SSE5A, MXCSR, CR4.OSXMMEXCPT, #XF bit 10 (IBS) instruction based sampling bit 9 (OSVW) OS-visible workaround bit 8 (3DNow!-) PREFETCH and PREFETCHW (K8 Rev G and K8L) bit 7 (MSSE) misaligned SSE, MXCSR.MM