AA-64 architecture two byte opcodes note: Except for the following differences in PM64 the two byte opcodes remain unchanged from IA-32.   modified two byte opcodes   opcode mnemonic 0Fh,34h SYSENTER 0Fh,35h SYSEXIT AMD64 processors don't support these.     new two byte opcodes   opcode mnemonic 0Fh,01h,F8h SWAPGS 0Fh,6Eh 66h,0Fh,6Eh 0Fh,7Eh 66h,0Fh,7Eh MOVD/MOVQ Pq,Eq MOVD/MOVQ Vo,Eq MOVD/MOVQ Eq,Pq MOVD/MOVQ Eq,Vq F3h,0Fh,2Ah F2h,0Fh,2Ah F3h,0Fh,2Ch F2h,0Fh,2Ch F3h,0Fh,2Dh F2h,0Fh,2Dh CVTSI2SS Vd,Eq CVTSI2SD Vq,Eq CVTTSS2SI Gq,Wd CVTTSD2SI Gq,Wq CVTSS2SI Gq,Wd CVTSD2SI Gq,Wq 0Fh,D7h 66h,0Fh,D7h PMOVMSKB Gq,PR PMOVMSKB Gq,VR 0Fh,50h 66h,0Fh,50h MOVMSKPS Gq,VR MOVMSKPD Gq,VR 0Fh,C3h MOVNTI Mq,Gq 0Fh,C7h,/1 CMPXCHG16B Mo CPUID indicates CMPXCHG16B support. In PM64 the default operand size is 32 bits. However, the following instructions default to a 64 bit operand size.   implicit RSP references   opcode mnemonic 0Fh,A0h 0Fh,A8h PUSH FS PUSH GS 0Fh,A1h 0Fh,A9h POP FS POP GS     near branches   opcode mnemonic 0Fh,80..8Fh Jcc Jz EM64T processors don't support a 66h prefix.     GDTR/IDTR loads/stores   opcode mnemonic 0Fh,01h,/0 SGDT Mt 0Fh,01h,/1 SIDT Mt 0Fh,01h,/2 LGDT Mt 0Fh,01h,/3 LIDT Mt A 66h prefix is silently ignored.     CRx/DRx/TRx moves   opcode mnemonic 0Fh,20h MOV Rq,Cq 0Fh,22h MOV Cq,Rq 0Fh,21h MOV Rq,Dq 0Fh,23h MOV Dq,Rq 0Fh,24h MOV Rq,Tq 0Fh,26h MOV Tq,Rq A 66h prefix is silently ignored.